AT32UC3A1256 Atmel Corporation, AT32UC3A1256 Datasheet - Page 318
AT32UC3A1256
Manufacturer Part Number
AT32UC3A1256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
Specifications of AT32UC3A1256
Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
69
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A1256-U
Manufacturer:
ATMEL
Quantity:
496
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- Current page: 318 of 826
- Download datasheet (11Mb)
32058K AVR32-01/12
Figure 26-19. FSK Modulator Output
26.7.4
Figure 26-20. Synchronous Mode Character Reception
26.7.4.1
Uptstream Frequencies
unipolar output
FSK Modulator
default polarity
[F0, F0+offset]
NRZ stream
Synchronous Receiver
Manchester
Receiver Operations
encoded
Output
data
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Sampling
Clock
RXD
Txd
1
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of
the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity
bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode
operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 26-20 on page 318
When a character reception is completed, it is transferred to the Receive Holding Register
(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while
the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into
RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register
(CR) with the RSTSTA (Reset Status) bit at 1.
Start
D0
D1
0
illustrates a character reception in synchronous mode.
D2
D3
D4
0
D5
D6
D7
Parity Bit
Stop Bit
1
AT32UC3A
318
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