AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet
AT32UC3A3128
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AT32UC3A3128 Summary of contents
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... Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface • One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities • ...
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Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and ...
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Description The AT32UC3A3/ complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on ...
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Overview 2.1 Block Diagram Figure 2-1. TCK TDO INTERFACE TDI TMS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N USB_VBIAS USB_VBUS DMFS, DMHS DPFS, DPHS INTERFACE ID VBOF 32KB RAM 32KB RAM DMACA AES CLK CMD[1..0] DATA[15.. EXTINT[7..0] ...
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Configuration Summary The table below lists all AT32UC3A3/A4 memory and package configurations: Table 2-1. Feature Flash SRAM HSB RAM EBI GPIO External Interrupts TWI USART Peripheral DMA Channels Generic DMA Channels SPI MCI slots High Speed USB AES (S ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 3-1. TFBGA144 Pinout (top view PX40 PB00 PA28 B PX10 PB11 ...
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Figure 3-2. LQFP144 Pinout PA21 109 PA22 110 PA23 111 PA24 112 PA20 113 PA19 114 PA18 115 PA17 116 GNDANA 117 VDDANA 118 PA25 119 PA26 120 PB05 121 PA00 122 PA01 123 PA05 124 PA03 125 PA04 126 ...
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Figure 3-3. VFBGA100 Pinout (top view PA28 PA27 B PB00 PB01 C PB11 PA31 D PX12 PX10 E PA02/ GNDIO (1) PX47 F PX19/ VDDIO (1) PX59 G PX05 PX01 H PX04 PX21 J PX03 PX24 K ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G ...
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Table 3-1. GPIO Controller Function Multiplexing G P BGA QFP BGA I 144 144 100 PIN PA28 PA29 PA30 PA31 ...
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Table 3-1. GPIO Controller Function Multiplexing G P BGA QFP BGA I 144 144 100 PIN O ( PX14 65 ( PX15 66 ( PX16 67 ( J10 PX17 ...
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Table 3-1. GPIO Controller Function Multiplexing G P BGA QFP BGA I 144 144 100 PIN PX52 103 ( PX53 104 E3 46 PX54 105 J5 79 PX55 106 J4 78 PX56 107 H4 ...
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TFBGA144 Note: 3.2.4 JTAG port connections Table 3-4. TFBGA144 K12 L12 J11 J10 3.2.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irre- spective of ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-6. Signal Description List Signal Name Function VDDIO I/O Power Supply VDDANA Analog Power Supply VDDIN Voltage Regulator Input Supply VDDCORE Voltage Regulator Output for ...
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Table 3-6. Signal Description List Signal Name Function RESET_N Reset Pin DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests EXTINT[7:0] External Interrupt Pins SCAN[7:0] Keypad Scan Pins NMI Non-Maskable Interrupt Pin General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] Parallel ...
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Table 3-6. Signal Description List Signal Name Function SDA10 SDRAM Address 10 Line SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDWE SDRAM Write Enable CLK Multimedia Card Clock CMD[1:0] Multimedia Card Command DATA[15:0] Multimedia Card Data SCLK Memory Stick Clock ...
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Table 3-6. Signal Description List Signal Name Function B0 Channel 0 Line B B1 Channel 1 Line B B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock ...
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Table 3-6. Signal Description List Signal Name Function DMHS USB High Speed Data - DPHS USB High Speed Data + USB_VBIAS USB VBIAS reference USB_VBUS USB VBUS signal VBOF USB VBUS on/off bus power control port ID ID Pin fo ...
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I/O Line Considerations 3.4.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven VDDIO, and has no pull-up resistor. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and ...
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Power Considerations 3.5.1 Power Supplies The AT32UC3A3 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC. Voltage is 3.3V nominal • VDDIN: Input voltage for the voltage ...
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Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some ...
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Figure 4-1. 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d 4.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in page 27. Table 4-2. Priority N/A N/A Mode ...
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All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103-191 192-255 4.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have ...
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The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter ...
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Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x8000_0000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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Module Configuration All AT32UC3A3 parts implement the CPU and Architecture Revision 2. 32072G–11/2011 34 ...
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... Memories 5.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix – 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 5 ...
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... Bus Monitor module - BUSMON MCI Mulitmedia Card Interface - MCI MSI Memory Stick Interface - MSI PDCA Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC Size Size AT32UC3A3128S AT32UC3A364S AT32UC3A3128 AT32UC3A364 AT32UC3A4128S AT32UC3A464S AT32UC3A4128 AT32UC3A464 32KByte 32KByte 32KByte 32KByte 64KByte 64KByte 64KByte 64KByte ...
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Table 5-2. Peripheral Address Mapping 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32072G–11/2011 PM Power Manager - PM RTC Real Time Counter - RTC WDT Watchdog Timer - WDT ...
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Table 5-2. Peripheral Address Mapping 0xFFFF5000 0xFFFF5400 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore ...
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Table 5-3. Port 2 3 32072G–11/2011 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Local Bus ...
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Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power controlled by the Power Manager. For specific details, refer to (PM)” on page 6.1 Starting of Clocks After power-up, the device will ...
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Power Manager (PM) Rev: 2.3.1.0 7.1 Features • Controls integrated oscillators and PLLs • Generates clocks and resets for digital logic • Supports 2 crystal oscillators 0.4-20MHz • Supports 2 PLLs 40-240MHz • Supports 32KHz ultra-low power oscillator • ...
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Block Diagram Figure 7-1. Voltage Regulator Calibration fuses Registers Brown-O ut Detector Power-O n Detector External Reset Pad 32072G–11/2011 Power Manager Block Diagram RCSYS O scillator 0 PLL0 PLL1 O scillator 1 OSC/PLL Control signals O scillator and PLL ...
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Product Dependencies 7.4.1 I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to their ...
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Figure 7-2. 7.5.3 32 KHz Oscillator Operation The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter. The oscillator is disabled by default, but ...
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Figure 7-3. Osc0 clock 0 1 Osc1 clock PLLOSC 7.5.4.1 Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator clock source. The PLLMUL and PLLDIV bitfields must ...
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The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre- quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2. The lock signal for each PLL is ...
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Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a pres- caler ...
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Mask ready flag Due to synchronization in the clock generator, there is a slight delay from a mask register is writ- ten until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ...
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Table 7-1. Sleep Modes Index Sleep Mode CPU 0 Idle Stop 1 Frozen Stop 2 Standby Stop 3 Stop Stop 4 DeepStop Stop 5 Static Stop The power level of the internal voltage regulator is also adjusted according to the ...
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Each generic clock module runs from either Oscillator PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also ...
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Generic clock implementation The generic clocks are allocated to different functions as shown in Table 7-2. Clock number 7.5.9 Divided PB Clocks The clock generator in the Power Manager provides divided PBA and ...
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Figure 7- r addition to the listed reset ...
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Table 7-4 on page 53 Table 7-4. Effect of the Different Reset Events CPU/HSB/PBA/PBB (excluding Power Manager) 32 KHz oscillator RTC control register GPLP registers Watchdog control register Voltage calibration register RCSYS Calibration register BOD control register BOD33 control register ...
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Brown-Out detector 3V3 The Brown-Out Detector 3V3 (BOD33) monitors one VDDIO supply pin and compares the sup- ply voltage to the brown-out detection 3V3 level, which is typically calibrated at 2V7. The BOD33 is enabled by default, but can ...
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User Interface Table 7-6. Offset 0x000 0x0004 0x008 0x00C 0x010 0x014 0x020 0x024 0x028 Oscillator 0 Control Register 0x02C Oscillator 1 Control Register 0x030 Oscillator 32 Control Register 0x040 PM Interrupt Enable Register 0x044 PM Interrupt Disable Register 0x048 ...
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Main Clock Control Register Name: MCCTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • OSC1EN: Oscillator 1 Enable 1: Oscillator 1 is ...
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Clock Select Register Name: CKSEL Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 PBBDIV - 23 22 PBADIV - CPUDIV - • PBBDIV: PBB Division Enable PBBDIV = 0: PBB clock ...
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Clock Mask Registers Name: CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x08-0x14 Reset Value: 0x00000003/0x00000FFF/0x001FFFFF/0x000003FF • MASK: Clock Mask If bit n is written to zero, the clock for module n is stopped. ...
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Table 7-7. Maskable module clocks in AT32UC3A3. Bit CPUMASK 16 SYSTIMER (compare/count registers clk 31:21 - Note: 32072G–11/2011 HSBMASK PBAMASK - TC0 - TC1 - ABDAC ( ...
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PLL Control Registers Name: PLL0,1 Access Type: Read/Write Offset: 0x20-0x24 Reset Value: 0x00000000 31 30 PLLTEST - • PLLTEST: PLL Test Reserved for internal use. Always write ...
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PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled. 32072G–11/2011 61 ...
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Oscillator 0/1 Control Registers Name: OSCCTRL0,1 Access Type: Read/Write Offset: 0x28-0x2C Reset Value: 0x00000000 • STARTUP: Oscillator Startup Time Select startup time for ...
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KHz Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 • STARTUP: Oscillator Startup Time Select startup time ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x40 Reset Value: 0x00000000 OSC0RDY MSKRDY Writing a one to a bit in this register will ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x44 Reset Value: 0x00000000 OSC0RDY MSKRDY Writing a one to a bit in this register will ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 OSC0RDY MSKRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 OSC0RDY MSKRDY • BOD33DET: Brown out detection This bit is set when ...
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LOCK1: PLL1 locked This bit is set when transition on the POSCSR.LOCK1 bit is detected: clock source. This bit is cleared when the corresponding bit in ICR is written to one. • LOCK0: PLL0 locked ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x50 Reset Value: 0x00000000 OSC0RDY MSKRDY Writing a zero to a bit in this register has ...
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Power and Oscillators Status Register Name: POSCSR Access Type: Read-only Offset: 0x54 Reset Value: 0x00000000 OSC0RDY MSKRDY • BOD33DET: Brown out 3V3 detection 0: No ...
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Generic Clock Control Register Name: GCCTRLx Access Type: Read/Write Offset: 0x60 - 0x74 Reset Value: 0x00000000 There is one GCCTRL register per generic clock in ...
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RC Oscillator Calibration Register Name: RCCR Access Type: Read/Write Offset: 0xC0 Reset Value: 0x00000000 • KEY: Register Write protection This field must be written twice, first with ...
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Bandgap Calibration Register Name: BGCR Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 • KEY: Register Write protection This field must be written twice, first ...
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PM Voltage Regulator Calibration Register Name: VREGCR Access Type: Read/Write Offset: 0xC8 Reset Value: 0x00000000 • KEY: Register Write protection This field must be written ...
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BOD Control Register Name: BOD Access Type: Read/Write Offset: 0xD0 Reset Value: 0x00000000 HYST • KEY: Register Write protection This field must be written twice, first ...
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BOD33 Control Register Name: BOD33 Access Type: Read/Write Offset: 0xD4 Reset Value: 0x0000010X • KEY: Register Write protection This field must be written twice, first ...
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Reset Cause Register Name: RCAUSE Access Type: Read-only Offset: 0x140 Reset Value: 0x00000000 CPUERR - • BOD33: Brown-out 3V3 Reset The CPU was reset due ...
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Asynchronous Wake Up Enable Name: AWEN Access Type: Read/Write Offset: 0x144 Reset Value • USB_WAKEN : Wake Up Enable Register Writing a ...
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General Purpose Low-power Register Name: GPLP Access Type: Read/Write Offset: 0x200 Reset Value: 0x00000000 These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset will ...
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Real Time Counter (RTC) Rev: 2.4.0.1 8.1 Features • 32-bit real-time counter with 16-bit prescaler • Clocked from RC oscillator or 32KHz oscillator • Long delays – Max timeout 272years • High resolution: Max count frequency 16KHz • Extremely ...
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Power Management The RTC remains operating in all sleep modes except Static mode. Interrupts are not available in DeepStop mode. 8.4.2 Clocks The RTC can use the system RC oscillator as clock source. This oscillator is always enabled whenever ...
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The RTC count value can be read from or written to the Value register (VAL). Due to synchroni- zation, continuous reading of the VAL register with the lowest prescaler setting will skip every other value. 8.5.1.3 RTC interrupt The RTC ...
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User Interface Table 8-1. RTC Register Memory Map Offset 0x00 Control Register 0x04 0x08 0x10 Interrupt Enable Register 0x14 Interrupt Disable Register 0x18 Interrupt Mask Register 0x1C Interrupt Status Register 0x20 Interrupt Clear Register 32072G–11/2011 Register Register Name Value ...
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Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00010000 • CLKEN: Clock Enable 1: The clock is enabled. 0: The ...
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Value Register Name: VAL Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 • VAL[31:0]: RTC Value This value is incremented on every rising edge of the source clock. 32072G–11/2011 29 28 ...
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Top Register Name: TOP Access Type: Read/Write Offset: 0x08 Reset Value: 0xFFFFFFFF • VAL[31:0]: RTC Top Value VAL wraps at this value. 32072G–11/2011 VAL[31:24 VAL[23:16] ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 • TOPI: Top Interrupt This bit is set when VAL ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Watchdog Timer (WDT) Rev: 2.4.0.1 9.1 Features • Watchdog timer counter with 32-bit prescaler • Clocked from the system RC oscillator (RCSYS) 9.2 Overview The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is clocked ...
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Functional Description The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field (PSEL) in the CTRL register ...
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Control Register Name: CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 • KEY: Write protection key This field must be written twice, first with ...
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Clear Register Name: CLR Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 • CLR: Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, ...
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Interrupt Controller (INTC) Rev: 1.0.1.5 10.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • groups of interrupts with ...
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Figure 10-1. INTC Block Diagram NMIREQ IREQ63 IREQ34 IREQ33 IREQ32 IREQ31 IREQ2 IREQ1 IREQ0 10.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 10.4.1 Power Management If the ...
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Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, ...
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pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 32072G–11/2011 99 ...
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User Interface Table 10-1. INTC Register Memory Map Offset Register 0x000 Interrupt Priority Register 0 0x004 Interrupt Priority Register 1 ... 0x0FC Interrupt Priority Register 63 0x100 Interrupt Request Register 0 0x104 Interrupt Request Register 1 ... 0x1FC Interrupt ...
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Interrupt Priority Registers Name: IPR0...IPR63 Access Type: Read/Write Offset: 0x000 - 0x0FC Reset Value: 0x00000000 31 30 INTLEVEL • INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt ...
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Interrupt Request Registers Name: IRR0...IRR63 Access Type: Read-only Offset: 0x0FF - 0x1FC Reset Value: N IRR[32*x+31] IRR[32*x+30] IRR[32*x+29 IRR[32*x+23] IRR[32*x+22] IRR[32*x+21 IRR[32*x+15] IRR[32*x+14] IRR[32*x+13 IRR[32*x+7] IRR[32*x+6] IRR[32*x+5] • IRR: Interrupt Request ...
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Interrupt Cause Registers Name: ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N • CAUSE: Interrupt Group Causing Interrupt of Priority ...
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Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports groups of interrupt requests. Each ...
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Table 10-2. 32072G–11/2011 Interrupt Request Signal Map 0 Peripheral DMA Controller 1 Peripheral DMA Controller 2 Peripheral DMA Controller 3 Peripheral DMA Controller 3 4 Peripheral DMA Controller 5 Peripheral DMA Controller 6 Peripheral DMA Controller 7 Peripheral DMA Controller ...
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Table 10-2. 32072G–11/2011 Interrupt Request Signal Map 0 DMA Controller 1 DMA Controller 22 2 DMA Controller 3 DMA Controller 4 DMA Controller 26 0 Memory Stick Interface 27 0 Two-wire Slave Interface 28 0 Two-wire Slave Interface Error code ...
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External Interrupt Controller (EIC) Rev: 2.4.0.0 11.1 Features • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on high or low level • Asynchronous interrupts for sleep modes ...
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Block Diagram Figure 11-1. EIC Block Diagram ...
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Clocks The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The filter and synchronous edge/level detector runs on a clock ...
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However, the corresponding bit in ISR will be set, and EIC_WAKE will be set. If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an external interrupt by ...
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Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in instead of the INTn bits. The NMI is non-maskable within the CPU in the sense that it ...
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Keypad scan support The External Interrupt Controller also includes support for keypad scanning. The keypad scan feature is compatible with keypads organized as rows and columns, where a row is shorted against a column when a key is pressed. ...
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User Interface Table 11-2. EIC Register Memory Map Offset 0x000 Interrupt Enable Register 0x004 Interrupt Disable Register 0x008 Interrupt Mask Register 0x00C Interrupt Status Register 0x010 Interrupt Clear Register 0x014 0x018 0x01C 0x020 0x024 0x028 Asynchronous Register 0x2C 0x030 ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The corresponding interrupt is ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt interrupt event has ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Mode Register Name: MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is edge ...
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Edge Register Name: EDGE Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt triggers on ...
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Level Register Name: LEVEL Access Type: Read/Write Offset: 0x01C Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt triggers on ...
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Filter Register Name: FILTER Access Type: Read/Write Offset: 0x020 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is not ...
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Test Register Name: TEST Access Type: Read/Write Offset: 0x024 Reset Value: 0x00000000 INT7 INT6 • TESTEN: Test Enable 0: This bit disables external interrupt test ...
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Asynchronous Register Name: ASYNC Access Type: Read/Write Offset: 0x028 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is synchronized ...
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Scan Register Name: SCAN Access Type: Read/Write Offset: 0x2C Reset Value: 0x0000000 • Keypad scanning is disabled 1: Keypad scanning is ...
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Enable Register Name: EN Access Type: Write-only Offset: 0x030 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this bit ...
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Disable Register Name: DIS Access Type: Write-only Offset: 0x034 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n Writing a zero to this bit ...
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Control Register Name: CTRL Access Type: Read-only Offset: 0x038 Reset Value: 0x00000000 INT7 INT6 • INTn: External Interrupt n 0: The corresponding external interrupt is ...
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Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 11-3. Feature ...
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Flash Controller (FLASHC) Rev: 2.2.1.3 12.1 Features • Controls flash block with dual read ports allowing staggered reads. • Supports 0 and 1 wait state bus access. • Allows interleaved burst reads for systems with one wait state, outputting ...
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Functional description 12.4.1 Bus interfaces The None has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash array and writes to the page buffer, and one Peripheral Bus (PB) interface for writing commands and control ...
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The flash controller supports flash blocks with up to 2^21 word addresses, as displayed in 12-1. Reading the memory space between address pw and 2^21-1 returns an undefined result. The User page is permanently mapped to word address 2^21. Table ...
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When writing to the page buffer, the PAGEN field in the FCMD register is updated with the page number corresponding to page address of the latest word written into the page buffer. The page buffer is also used for writes ...
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CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter sleep mode after writing to FCMD polling FSR for command completion. This polling will result in an access pattern with IDLE ...
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Lock Error: The page to be programmed belongs to a locked region. A command must be executed to unlock the corresponding region before programming can start. 12.5.2 Erase All operation The entire memory is erased if the Erase All ...
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Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions.: Table 12-2. General- Purpose fuse number 15:0 16 19:17 The BOOTPROT fuses protects the following ...
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To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these com- mands, together with the number of the fuse to write/erase, performs the ...
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User interface 12.8.1 Address map The following addresses are used by the None. All offsets are relative to the base address allo- cated to the flash controller. Table 12-4. Offset 0x0 0x4 0x8 0xc 0x10 (*) The value of ...
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Flash Control Register Name: FCR Access Type: Read/Write Offset: 0x00 Reset value: 0x00000000 FWS • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does ...
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Flash Command Register Name: FCMD Access Type: Read/Write Offset: 0x04 Reset value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to ...
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Table 12-5. Set of commands Command Quick Page Read User Page Read High Speed Enable Read High Speed Disable • PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order ...
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Flash Status Register Name: FSR Access Type: Read/Write Offset: 0x08 Reset value: 0x00000000 31 30 LOCK15 LOCK14 23 22 LOCK7 LOCK6 15 14 FSZ • FRDY: Flash Ready Status 0: The flash controller is busy and ...
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FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 12-7. Flash size FSZ Flash Size 0 32 KByte 1 64 kByte 2 128 kByte 3 256 ...
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Flash General Purpose Fuse Register High Name: FGPFRHI Access Type: Read Offset: 0x0C Reset value: N GPF63 GPF62 23 22 GPF55 GPF54 15 14 GPF47 GPF46 7 6 GPF39 GPF38 This register is only used in systems ...
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Flash General Purpose Fuse Register Low Name: FGPFRLO Access Type: Read Offset: 0x10 Reset value: N GPF31 GPF30 23 22 GPF23 GPF22 15 14 GPF15 GPF14 7 6 GPF07 GPF06 • GPFxx: General Purpose Fuse xx 0: ...
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Fuses Settings The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO) of the Flash Controller (FLASHC). Some of the FGPFRLO fuses have defined meanings outside ...
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GPF30 reserved for future use • GPF29 reserved for future use • BODEN fuses set to 0b11. BOD is disabled. • BODHYST fuse set to 0b1. The BOD hystersis is enabled. • BODLEVEL fuses set to 0b111111. This is ...
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HSB Bus Matrix (HMATRIX) Rev: 2.3.0.2 13.1 Features • User Interface on peripheral bus • Configurable Number of Masters (Up to sixteen) • Configurable Number of Slaves (Up to sixteen) • One Decoder for Each Master • • Programmable ...
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At the end of the current access other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and ...
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End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is man- aged differently for undefined length burst. ...
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This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform ...
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User Interface Table 13-1. HMATRIX Register Memory Map Offset Register 0x0000 Master Configuration Register 0 0x0004 Master Configuration Register 1 0x0008 Master Configuration Register 2 0x000C Master Configuration Register 3 0x0010 Master Configuration Register 4 0x0014 Master Configuration Register ...
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Table 13-1. HMATRIX Register Memory Map (Continued) Offset Register 0x008C Priority Register B for Slave 1 0x0090 Priority Register A for Slave 2 0x0094 Priority Register B for Slave 2 0x0098 Priority Register A for Slave 3 0x009C Priority Register ...
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Table 13-1. HMATRIX Register Memory Map (Continued) Offset Register 0x012C Special Function Register 7 0x0130 Special Function Register 8 0x0134 Special Function Register 9 0x0138 Special Function Register 10 0x013C Special Function Register 11 0x0140 Special Function Register 12 0x0144 ...
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Master Configuration Registers Name: MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 – – – – – – – – • ULBT: Undefined Length Burst Type 0: Infinite ...
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Slave Configuration Registers Name: SCFG0...SCFG15 Access Type: Read/Write Offset: 0x40 - 0x7C Reset Value: 0x00000010 31 30 – – – – – – • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority ...
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Priority Registers A For Slaves Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 – – – – – – – – • MxPR: Master x Priority Fixed priority of ...
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Priority Registers B For Slaves Name: PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 – – – – – – – – • MxPR: Master x Priority Fixed priority of ...
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Special Function Registers Name: Access Type: Offset: 0x110 - 0x115 Reset Value • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those ...
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Bus Matrix Connections Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing ...
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Figure 13-1. HMATRIX Master / Slave Connections CPU Data 0 CPU 1 Instruction CPU SAB 2 PDCA 3 DMACA 4 Master 0 DMACA 5 Master 1 USBB 6 DMA 32072G–11/2011 HMATRIX SLAVES ...
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External Bus Interface (EBI) Rev.: 1.7.0.1 14.1 Features • Optimized for application memory space support • Integrates three external memory controllers: – Static Memory Controller (SMC) – SDRAM Controller (SDRAMC) – Error Corrected Code (ECCHRS) controller • Additional logic ...
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Block Diagram Figure 14-1. EBI Block Diagram HMATRIX SFR registers Address Decoders HSB-PB Bridge 32072G–11/2011 INTC SDRAMC_irq EBI SDRAM HSB Controller Static Memory Controller ECCHRS Controller NAND Flash SmartMedia Logic Compact FLash Logic Chip Select Assignor Peripheral Bus ECCHRS_irq ...
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I/O Lines Description Table 14-1. Pin Name DATA[15:0] ADDR[1] ADDR[12] ADDR[15] ADDR[23:18] NCS[0] NWAIT SDCK SDCKE SDWE SDA10 RAS - CAS CFCE1 - CFCE2 CFRNW NANDOE NANDWE NCS[1] ADDR[0] ADDR[11:2] ADDR[14:13] ADDR[16] 32072G–11/2011 EBI I/O Lines Description Alternate Name ...
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Pin Name ADDR[17] NRD NWE0 NCS[4] NCS[5] NCS[2] NCS[3] NWE1 14.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 14.5.1 I/O Lines The pins used for interfacing the ...
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CLK_ECCHRS Refer to Table 14-2. Clocks name CLK_EBI CLK_SDRAMC CLK_SMC CLK_ECCHRS 14.5.4 Interrupts The EBI interface has two interrupt lines connected to the Interrupt Controller: • SDRAMC_IRQ: Interrupt signal coming from the SDRAMC • ECCHRS_IRQ: Interrupt signal coming from ...
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Table 14-3. SFR6 Bit Number 14.6 Functional Description The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the exter- nal memories or peripheral devices. It controls the waveforms and the parameters of the external address, ...
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CompactFlash Support The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the SMC on the NCS[4] and/or NCS[5] address space. Writing to the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits the appropriate value enables ...
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NCS pin (NCS[4] or NCS[5]). The Data Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address space must be written as shown in NBS1 ...
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Figure 14-3. CompactFlash Read/Write Control Signals Table 14-6. Mode Base Address Attribute Memory I/O Mode (Write operations) Common Memory I/O Mode (Read operations) 14.6.5.4 Multiplexing of CompactFlash signals on EBI pins Table 14-7 on page 170 logic signals with other ...
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Table 14-8. Pins NRD NWE0 NWE1 CFRNW 14.6.5.5 Application example Figure 14-4 on page 171 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output enable of the buffers between ...
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Figure 14-5. CompactFlash Application Example without I/O mode 14.6.6 SmartMedia and NAND Flash Support The EBI integrates circuitry that interfaces to SmartMedia and NAND Flash devices. The NAND Flash logic is driven by the Static Memory Controller on the NCS[2] ...
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Figure 14-6. NAND Flash Signal Multiplexing on EBI Pins 14.6.6.1 NAND Flash signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. ...
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Application Example 14.7.1 Hardware Interface Table 14-9. Pins name Controller DATA[7:0] DATA[15:0 ADDR[0] ADDR[1] ADDR[23:2] NCS[0] - NCS[5] NRD NWE0 NWE1 Note: Table 14-10. EBI Pins and External Devices Connections Pins name Controller DATA[7:0] DATA[15:8] ADDR[0] ADDR[1] ADDR[10:2] ADDR[11] ...
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Table 14-10. EBI Pins and External Devices Connections (Continued) Pins name Controller ADDR[21] ADDR[22] NCS[0] NCS[1] NCS[2] NCS[3] NCS[4] NCS[5] NANDOE NANDWE NRD NWE0 NWE1 CFRNW CFCE1 CFCE2 SDCK SDCKE RAS CAS SDWE NWAIT (2) Pxx (2) Pxx Note: 32072G–11/2011 ...
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Connection Examples Figure 14-8 on page devices. Figure 14-8. EBI Connections to Memory Devices EBI 32072G–11/2011 176shows an example of connections between the EBI and external DATA[15:0] RAS SDRAM CAS SDCK 2Mx8 DATA[7:0] SDCKE D[7:0] SDWE ADDR[0] CS SDCK ...
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Static Memory Controller (SMC) Rev. 1.0.6.5 15.1 Features • 6 chip selects available • 16-Mbytes address space per chip select • 16-bit data bus • Word, halfword, byte transfers • Byte write or byte select lines • ...
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Block Diagram Figure 15-1. SMC Block Diagram (AD_MSB=23) SMC HMatrix Chip Select Power CLK_SMC Manager Peripheral Bus 15.4 I/O Lines Description Table 15-1. Pin Name NCS[5:0] NRD NWR0/NWE A0/NBS0 NWR1/NBS1 A[23:2] D[15:0] NWAIT 15.5 Product Dependencies In order to ...
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I/O Lines The SMC signals pass through the External Bus Interface (EBI) module where they are multi- plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to SMC signals to their peripheral function. ...
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Figure 15-3. Memory Connections for Six External Devices NCS[0] - NCS[5] NRD SMC NWE A[AD_MSB:0] D[15:0] 15.6.3 Connection to External Devices 15.6.3.1 Data bus width A data bus width bits can be selected for each chip ...
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Figure 15-5. •Byte write access The byte write access mode supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in byte write access mode. • ...
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Figure 15-6. •Signal multiplexing Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To save I/Os at the external bus interface, control signals at the SMC interface are multiplexed. For 16-bit devices, bit ...
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NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..5] chip select lines. 15.6.4.1 Read waveforms The read cycle is shown on The read cycle starts with ...
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NCSRDSETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCSRDHOLD: the NCS ...
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Figure 15-8. No Setup, No Hold on NRD, and NCS Read Signals CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 D[15:0] • Null Pulse Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads ...
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Figure 15-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 D[15:0] •Read is controlled by NCS (MODE.READMODE = 0) Figure 15-10 on page 187 t after the falling ...
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Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 D[15:0] 15.6.4.3 Write waveforms The write protocol is similar to the read protocol depicted in write ...
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Figure 15-11. Write Cycle CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 •Write cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to ...
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If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see 189). However, for devices that perform write operations ...
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Figure 15-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 D[15:0] •Write is controlled by NCS (MODE.WRITEMODE = 0) Figure 15-14 on page 190 written to zero. The data ...
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Coding timing parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type. The Setup register (SETUP) groups the definition of all setup parameters: • NRDSETUP, NCSRDSETUP, NWESETUP, and ...
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Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 15.6.5.1 Chip select wait states The SMC always inserts an idle cycle between two transfers on separate chip ...
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An early read wait state is automatically inserted if at least one of the following conditions is valid: • if the write controlling signal has no hold time and the read controlling signal has no setup time • in NCS ...
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Figure 15-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read A[AD_MSB:2] NBS0, NBS1, 32072G–11/2011 with No Setup. CLK_SMC A0, A1 NWE NRD No hold D[15:0] Write cycle (WRITEMODE=0) No setup Read cycle Early Read ...
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Figure 15-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read Internal write controlling signal external write controlling 15.6.5.3 Reload user configuration wait state The user may change any of the configuration parameters by writing the ...
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A reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see 15.6.5.4 Read to write wait state Due to an internal mechanism, ...
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Figure 15-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2) Figure 15-20. TDF Period in NCS Controlled Read Operation (TDFCYCLES = 3) 32072G–11/2011 CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 NRD NCS t PACC D[15:0] NRD controlled read operation ...
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TDF optimization enabled (MODE.TDFMODE = 1) When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to ...
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TDF optimization. Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif- ferent Chip Selects. CLK_SMC A[AD_MSB:2] NBS0, ...
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Figure 15-24. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Read and Write accesses on the Same Chip Select. CLK_SMC A[AD_MSB:2] NBS0, NBS1, A0, A1 Read1 controlling signal(NRD) Write2 controlling signal(NWE) D[15:0] Read1 cycle TDFCYCLES = 5 15.6.7 ...