AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 58

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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58
AVR32
The following fields exist in PCCR, see
Table 7-1.
Bit
23:18
17:12
10:8
6:4
3
2
1
0
Other
Access
Read/write
Read/write
Read/write
Read/write
Read/write
Read-0/write
Read-0/write
Read/write
Read-0/write-
0
Performance counter control register
Name
CONF1
CONF0
F
IE
S
C
R
E
-
Description
Configures which events to count with PCNT1. See Table 7-2 for a
legend.
Configures which events to count with PCNT0. See Table 7-2 for a
legend.
Interrupt flag. If read as 1, the corresponding overflow has
occurred. Bit 8 corresponds to PCCNT.
Bit 9 corresponds to PCNT0.
Bit 10 corresponds to PCNT1.
Flags are cleared by writing a 1 to the flag.
Interrupt enable. If set, an overflow of the corresponding counter
will cause an interrupt request.
Bit 4 corresponds to PCCNT.
Bit 5 corresponds to PCNT0.
Bit 6 corresponds to PCNT1.
Clock counter scaler. If set, the clock counter increments once
every 64’th clock cycle. This expands the period-to-overflow to 2
cycles.
Clock counter reset. If written to 1, the clock counter will be reset.
Performance counter reset. If written to 1, all three counters will be
reset.
Clock counter enable. If set, all three counters will count their
configured events. If cleared, the counters are disabled and will
not count.
Unused. Read as 0. Should be written as 0.
Table 7-1 on page
58.
32000D–04/2011
38

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