AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 502
AT32UC3B0512AU
Manufacturer Part Number
AT32UC3B0512AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A0128AU.pdf
(2 pages)
5.AT32UC3B0128.pdf
(684 pages)
6.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0512AU
Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512AU-Z2U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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23.7.8
Name:
Access Type:
Offset:
Reset Value:
Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
• MTIOB: TIOB Mirror
• MTIOA: TIOA Mirror
• CLKSTA: Clock Enabling Status
• ETRGS: External Trigger Status
• LDRBS: RB Loading Status
• LDRAS: RA Loading Status
• CPCS: RC Compare Status
32059L–AVR32–01/2012
ETRGS
31
23
15
7
-
-
-
1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven
high.
0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven
low.
1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven
high.
0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven
low.
1: This bit is set when the clock is enabled.
0: This bit is cleared when the clock is disabled.
1: This bit is set when an external trigger has occurred.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RC Compare has occurred.
0: This bit is cleared when the SR register is read.
Channel Status Register
LDRBS
30
22
14
6
-
-
-
SR
Read-only
0x20 + n * 0x40
0x00000000
LDRAS
29
21
13
5
-
-
-
CPCS
28
20
12
4
-
-
-
CPBS
27
19
11
3
-
-
-
MTIOB
CPAS
26
18
10
2
-
-
LOVRS
MTIOA
25
17
9
1
-
-
CLKSTA
COVFS
24
16
8
0
-
-
502
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