AT32UC3B064 Atmel Corporation, AT32UC3B064 Datasheet - Page 516
AT32UC3B064
Manufacturer Part Number
AT32UC3B064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B064
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
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24.6
24.6.1
32059L–AVR32–01/2012
Functional Description
PWM Clock Generator
The PWM macrocell is primarily composed of a clock generator module and
Figure 24-2. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must ensure that the PWM clock in
the Power Manager is enabled.
The PWM macrocell master clock, CLK_PWM, is divided in the clock generator module to pro-
vide different clocks available for all channels. Each channel can independently select one of the
– Clocked by the system clock, CLK_PWM, the clock generator module provides 13
– Each channel can independently choose one of the clock generator outputs.
– Each channel generates an output waveform with attributes that can be defined
clocks.
independently for each channel through the user interface registers.
CLK_PWM
modulo n
Counter
PREA
PREB
MR
MR
Divider A
Divider B
DIVA
DIVB
CLK_PWM/32
CLK_PWM/2
CLK_PWM/16
CLK_PWM/64
CLK_PWM/128
CLK_PWM/256
CLK_PWM/512
CLK_PWM/1024
CLK_PWM
CLK_PWM/4
CLK_PWM/8
clk B
clk A
7
channels.
516
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