AT32UC3B164 Atmel Corporation, AT32UC3B164 Datasheet - Page 173
AT32UC3B164
Manufacturer Part Number
AT32UC3B164
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B164
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 173 of 684
- Download datasheet (11Mb)
17.5.1
17.5.1.1
17.5.1.2
17.5.1.3
32059L–AVR32–01/2012
Basic Operation
Output control
I/O Line or peripheral function selection
Peripheral selection
Figure 17-2. Overview of the GPIO Pad Connections
When a pin is multiplexed with one or more peripheral functions, the selection is controlled with
the GPIO Enable Register (GPER). If a bit in GPER is written to one, the corresponding pin is
controlled by the GPIO. If a bit is written to zero, the corresponding pin is controlled by a periph-
eral function.
The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection
is performed by accessing Peripheral Mux Register 0 (PMR0) and Peripheral Mux Register 1
(PMR1).
When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is writ-
ten to zero, the drive of the I/O line is controlled by the peripheral. The peripheral, depending on
the value in PMR0 and PMR1, determines whether the pin is driven or not.
When the I/O line is controlled by the GPIO, the value of the Output Driver Enable Register
(ODER) determines if the pin is driven or not. When a bit in this register is written to one, the cor-
Periph. A output enable
Periph. B output enable
Periph. C output enable
Periph. D output enable
Periph. A output data
Periph. B output data
Periph. C output data
Periph. D output data
Periph. A input data
Periph. B input data
Periph. C input data
Periph. D input data
PMR1
PMR0
ODER
OVR
GPER
Glitch Filter
PVR
GFER
1
0
0
1
0
1
Edge Detector
IMR1
IMR0
IER
1
0
PUER
Interrupt Request
PAD
173
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