AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 100
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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8.6.8
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
32117C–AVR-08/11
PLLCOUNT: PLL Count
PLLMUL: PLL Multiply Factor
PLLDIV: PLL Division Factor
PLLOPT: PLL Option
31
23
15
7
-
-
-
-
Specifies the number of slow clock cycles before ISR.LOCKn is set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
These fields determine the ratio of the output frequency of the internal VCO of the PLL (f
According to PLLOPT[1] bit, it gives the following PLL frequency value f
PLLDIV gives also the input frequency of the PLL (f
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range.
PLLOPT[1]: Enable the extra output divider.
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).
PLL Control Register
if the PLLDIV field is set to 0: f
if the PLLDIV field is greater than 0: f
f
f
if the PLLOPT[1] bit is set to 0: f
if the PLLOPT[1] bit is set to 1: f
Note that the PLLMUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.
vco
vco
= (PLLMUL+1) / (PLLDIV) * f
= 2 * (PLLMUL+1) * f
30
22
14
PLL0,1
Read/Write
0x001C,0x0020
0x00000000
6
-
-
-
-
osc
if PLLDIV = 0
29
21
13
5
-
-
IN
= f
PLL
PLL
osc
OSC
= f
= f
if PLLDIV > 0
IN
VCO
VCO
= f
OSC
PLLOPT
/ 2
28
20
12
/ (2 * PLLDIV)
4
-
-
IN
):
27
19
11
3
PLLCOUNT
PLL
:
26
18
10
2
vco
PLLMUL
PLLOSC
PLLDIV
) to the source oscillator frequency:
25
17
9
1
AT32UC3C
PLLEN
24
16
8
0
100
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