AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 1109
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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36.6.5
36.6.6
32117C–AVR-08/11
ADC Clock Configuration (CKDIV)
ADC Multiplexers Settle Time
Figure 36-5. Using FRM and Converting at Full Speed
The clock frequency range for the ADC is [1.5 MHz - 32 KHz]. Since the ADC interface uses the
system clock up to the PB maximum frequency, a clock downscale must be done if a higher fre-
quency system clock is used. This scaling may also be done in order to slow down the ADC
conversions or increase the S/H time, without affecting the system clock. The downscale is done
by writing the maximum counter value in the Counter Value (CNT) field of the CKDIV register,
with a possible division factor from 1 to 512 giving the following transfer function:
T(CkADC)= T(CkPB)
setting the ADCEN bit in the CFG register.
Figure 36-6. Clock Generator Block Diagram
In addition when CKDIV is written, the internal counter is reset to avoid rollover phenomena: DO
NOT WRITE CKDIV WHEN PERFORMING CONVERSIONS.
F(CkPB) should at least be 4 times greater than F(CkADC) to make the ADC controller work
properly.
By default, channel multiplexers settle time is set to half a PB clock period. If operating with a
high PB clock frequency, then MUX settle time can be increased to achieve a 1.5 PB clock peri-
ods settle time by writing a one in the MUXSET field in the CFG register. For more information,
please refer to the ADC electrical characteristics.
[115 KHz - PB max
CkPB ADCIFA
frequency]
·
((CNT + 1)
DIVIDE BY CNT
·
2). The divider is enabled as soon as the ADC is enabled by
CKDIV :
/2
[32 KHz - 2 MHz]
AT32UC3C
CkADC
1109
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