AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 884
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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32.6.2.12
32.6.2.13
32117C–AVR-08/11
Multi packet mode and single packet mode.
Management of control endpoints
• Overview
• Control write
Single packet mode is the default mode where one USB packet is managed per bank.
The multi-packet mode allows the user to manage data exceeding the maximum endpoint size
(UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention.
This mode can also be coupled with the ping-pong mode.
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn is irrelevant for control endpoints. The user should
therefore never use it for these endpoints. When read, this value is always zero.
Control endpoints are managed using:
Figure 32-9 on page 885
ler will not necessarily send a NAK on the first IN token:
• For an OUT endpoint, the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE field should be
• For an IN endpoint, the EPn_PCKSIZE_BK0/1.BYTE_COUNT field should be configured
• The RXSTPI bit: is set when a new SETUP packet is received. This has to be cleared by
• The RXOUTI bit: is set when a new OUT packet is received. This has to be cleared by
• The Transmitted IN Data Interrupt (TXINI) bit: is set when the current bank is ready to accept
• If the user knows the exact number of descriptor bytes that will be read, the status stage can
• Alternatively the bytes can be read until the NAKed IN Interrupt (NAKINI) is triggered,
configured correctly to enable the multi-packet mode. See
endpoints” on page
initialized to 0.
correctly to enable the multi-packet mode.
887. For single packet mode, the BYTE_COUNT should be less than EPSIZE.
firmware in order to acknowledge the packet and to free the bank.
firmware in order to acknowledge the packet and to free the bank.
a new IN packet. This has to be cleared by firmware in order to send the packet.
be predicted, and a zero-length packet can be sent after the next IN token.
notifying that all bytes are sent by the host and that the transaction is now in the status stage.
889. For single packet mode, the MULTI_PACKET_SIZE should be
shows a control write transaction. During the status stage, the control-
See”Multi packet mode for IN endpoints” on page
”Multi packet mode for OUT
AT32UC3C
884
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