AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 111

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.3.6
Table 9-6.
32000D–04/2011
Mnemonics
bfexts
bfextu
bfins
bld
brev
bst
casts.b
casts.h
castu.b
castu.h
cbr
clz
sbr
swap.b
swap.bh
swap.h
Bit Operations
Bit Operations
E
E
E
E
C
E
C
C
C
C
C
E
C
C
C
C
Operands / Syntax
Rd, Rs, o5, w5
Rd, Rs, o5, w5
Rd, Rs, o5, w5
Rd, bp
Rd
Rd, bp
Rd
Rd
Rd
Rd
Rd, bp
Rd, Rs
Rd, bp
Rd
Rd
Rd
Description
Extract and sign-extend the w5 bits in Rs
starting at bit-offset o5 to Rd.
Extract and zero-extend the w5 bits in Rs
starting at bit-offset o5 to Rd.
Insert the lower w5 bits of Rs in Rd at bit-
offset o5.
Bit load.
Bit reverse.
Bit store.
Typecast byte to signed word.
Typecast halfword to signed word.
Typecast byte to unsigned word.
Typecast halfword to unsigned word.
Clear bit in register.
Count leading zeros.
Set bit in register.
Swap bytes in register.
Swap bytes in each halfword.
Swap halfwords in register.
Rd ← SE(Rd[15:0])
Rd ← ZE(Rd[7:0])
Rd ← ZE(Rd[15:0])
Rd[bp5] ← 0
Operation
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
C ← Rd[bp5]
Z ← Rd[bp5]
Rd[0:31] ← Rd[31:0]
Rd[bp5] ← C
Rd ← SE(Rd[7:0])
See Instruction Set Reference
Rd[bp5] ← 1
Rd[31:24] ← Rd[7:0],
Rd[23:16] ← Rd[15:8],
Rd[15:8] ← Rd[23:16],
Rd[7:0] ← Rd[31:24]
Rd[31:24] ← Rd[23:16],
Rd[23:16] ← Rd[31:24],
Rd[15:8] ← Rd[7:0],
Rd[7:0] ← Rd[15:8]
Rd[31:16] ← Rd[15:0],
Rd[15:0] ← Rd[31:16]
AVR32
Rev
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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