AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 10

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AT32UC3C1512C

Manufacturer Part Number
AT32UC3C1512C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C1512C

Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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2.7
10
The Stack Pointer
AVR32
rations of shadowed registers. This allows for maximum flexibility in targeting the processor for
different application, see
Figure 2-4.
Three different shadowing schemes are offered, small, half and full, ranging from no general
registers shadowed to all general registers shadowed, see
Figure 2-5.
Since the Stack Pointer (SP) is located in the register file, it can be addressed as an ordinary
register. This simplifies allocation and access of local variables and parameters. The Stack
Pointer is also used implicitly by several instructions.
The system modes have a shadowed stack pointer different from the application mode stack
pointer. This allows having a separate system stack.
Application
Bit 31
SP_APP
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Supervisor
Bit 31
RSR_SUP
RAR_SUP
A typical AVR32B register file implementation
AVR32 offers three different models for shadowed registers.
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Small
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
Figure 2-4 on page
PC
LR
INT0
Bit 31
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
RSR_INT0
RAR_INT0
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Bit 0
INT1
Bit 31
RSR_INT1
RAR_INT1
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Half
Bit 31
R12_INTx
R11_INTx
R10_INTx
Bit 0
LR_INTx
R9_INTx
R8_INTx
SP_SYS
FINTPC
10.
SMPC
PC
R7
R6
R5
R4
R3
R2
R1
R0
INT2
Bit 31
RSR_INT2
RAR_INT2
R12_INT2
R11_INT2
R10_INT2
Bit 0
LR_INT2
SP_SYS
R9_INT2
R8_INT2
FINTPC
SMPC
PC
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Figure 2-5 on page
INT3
Bit 31
Full
Bit 31
RSR_INT3
RAR_INT3
R12_INT3
R11_INT3
R10_INT3
LR_INT3
R9_INT3
R8_INT3
R7_INT3
R6_INT3
R5_INT3
R4_INT3
R3_INT3
R2_INT3
R1_INT3
R0_INT3
SP_SYS
INT0PC
INT1PC
FINTPC
R12_INTx
R11_INTx
R10_INTx
SMPC
LR_INTx
R9_INTx
R8_INTx
R7_INTx
R6_INTx
R5_INTx
R4_INTx
R3_INTx
R2_INTx
R1_INTx
R0_INTx
SP_SYS
FINTPC
PC
SR
INT0PC
INT1PC
SMPC
PC
Bit 0
Bit 0
Exception
Bit 31
RSR_EX
RAR_EX
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
10.
Bit 0
32000D–04/2011
NMI
Bit 31
RSR_NMI
RAR_NMI
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0

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