AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 259

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32000D–04/2011
PADDH.{UB/SH} – Packed Addition with Halving
Architecture revision:
Architecture revision1 and higher.
Description
Perform addition of four pairs of packed unsigned bytes (paddh.ub) or two pairs of packed signed
halfwords (paddh.sh) with a halving of the result to prevent any overflows from occuring.
Operation:
I.
II.
Syntax:
I.
II.
Operands:
I, II.
Status Flags:
Opcode:
31
31
1
1
15
0
15
0
Rd[31:24] ← LSR(ZE(Rx[31:24], 9) + ZE(Ry[31:24], 9), 1) ;
Rd[23:16] ← LSR(ZE(Rx[23:16], 9) + ZE(Ry[23:16], 9), 1);
Rd[15:8] ← LSR(ZE(Rx[15:8], 9) + ZE(Ry[15:8], 9), 1);
Rd[7:0] ← LSR(ZE(Rx[7:0], 9) + ZE(Ry[7:0], 9), 1);
Rd[31:16] ← ASR(SE(Rx[31:16], 17) + SE(Ry[31:16], 17), 1);
Rd[15:0] ← ASR(SE(Rx[15:0], 17) + SE(Ry[15:0], 17), 1);
paddh.ub
paddh.sh
{d, x, y} ∈ {0, 1, …, 15}
Q:
V:
N:
Z:
C:
Format I:
Format II:
1
1
0
0
29
29
1
1
1
1
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
28
28
0
0
Rd, Rx, Ry
Rd, Rx, Ry
0
0
Rx
Rx
0
0
25
25
0
1
24
0
24
0
0
1
0
0
1
0
1
1
0
0
0
0
0
1
4
4
20
0
20
0
0
0
3
3
19
19
Ry
Ry
Rd
Rd
AVR32
0
0
16
16
259