AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 38

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AT32UC3C1512C

Manufacturer Part Number
AT32UC3C1512C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C1512C

Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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5.2.1
5.2.2
38
AVR32
Virtual Memory Models
MMU interface registers
The MMU provides two different virtual memory models, selected by the Mode (M) bit in the
MMU Control Register:
In shared virtual memory, the virtual address uniquely identifies which physical address it should
be mapped to. Two different processes addressing the same virtual address will always access
the same physical address. In other words, the Virtual Page Number (VPN) section of the virtual
address uniquely specifies the Physical Frame Number (PFN) section in the physical address.
In private virtual memory, each process has its own virtual memory space. This is implemented
by using both the VPN and the Application Space Identifier (ASID) of the current process when
searching the TLB for a match. Each process has a unique ASID. Therefore, two different pro-
cesses accessing the same VPN won’t hit the same TLB entry, since their ASID is different.
Pages can be shared between processes in private virtual mode by setting the Global (G) bit in
the page table entry. This will disable the ASID check in the TLB search, causing the VPN sec-
tion uniquely to identify the PFN for the particular page.
The following registers are used to control the MMU, and provide the interface between the
MMU and the operating system. Most registers can be altered both by the application software
(by writing to them) and by hardware when an exception occurs. All the registers are mapped
into the System Register space, their addresses are presented in
ters” on page
Figure 5-3.
• Shared virtual memory, where the same virtual address space is shared between all
• Private virtual memory, where each process has its own virtual address space
processes
14. The MMU interface registers are shown in
The MMU interface registers
T L B E H I
T L B E L O
P T B R
T L B E A R
M M U C R
T L B A R L O / T L B A R H I
3 1
3 1
3 1
3 1
3 1
3 1
IR P
2 6
2 5
IL A
V P N
P F N
2 0
1 9
T L B A R L O / T L B A R H I
D R P
T L B E A R
P T B R
1 4
1 3
D L A
1 0
1 0
Figure
V
C
9
9
8
8
G
8
I
7
7
B
7
6
-
Section 2.11 “System regis-
5-3.
A P
5
A S ID
4
4
S
3
3
N
S Z
2
2
I
1
D
M
1
W
E
0
0
0
0
0
0
32000D–04/2011

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