AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 9

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2.6.2
32000D–04/2011
Register File in AVR32B
Figure 2-2.
The AVR32B allows separate register files for the interrupt and exception modes, see
on page
to speed up interrupt handling. The shadowed registers are automatically mapped in depending
on the current execution mode.
All contexts, except Application, have a dedicated Return Status Register (RSR) and Return
Address Register (RAR). The RSR registers are used for storing the Status Register value in the
context to return to. The RAR registers are used for storing the address in the context to return
to. The RSR and RAR registers eliminates the need to temporarily store the Status Register and
return address to stack when entering a new context.
Figure 2-3.
The register file is designed with an implementation specific part and an architectural defined
part. Depending on the implementation, each of the interrupt modes can have different configu-
Application
Bit 31
Application
Bit 31
SP_APP
SP_APP
INT0PC
INT1PC
FINTPC
INT0PC
INT1PC
FINTPC
SMPC
SMPC
R12
R11
R10
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Bit 0
9. These modes have a number of implementation defined shadowed registers in order
Supervisor
Bit 31
Supervisor
Bit 31
RSR_SUP
RAR_SUP
Register File in AVR32A
Register File in AVR32B
SP_SYS
SP_SYS
INT0PC
INT1PC
FINTPC
INT0PC
INT1PC
FINTPC
SMPC
SMPC
R12
R11
R10
R12
R11
R10
PC
LR
SR
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Bit 0
INT0
Bit 31
INT0
Bit 31
LR / LR_INT0
(implementation
RSR_INT0
RAR_INT0
registers
SP_SYS
SP_SYS
FINTPC
INT0PC
INT1PC
banked
SMPC
defined)
R12
R11
R10
PC
SR
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Bit 0
INT1
Bit 31
INT1
Bit 31
LR / LR_INT1
(implementation
RSR_INT1
RAR_INT1
registers
SP_SYS
SP_SYS
INT0PC
INT1PC
FINTPC
banked
SMPC
defined)
R12
R11
R10
PC
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
SR
Bit 0
Bit 0
INT2
Bit 31
INT2
Bit 31
LR / LR_INT2
(implementation
RSR_INT2
RAR_INT2
registers
SP_SYS
SP_SYS
INT0PC
INT1PC
FINTPC
banked
SMPC
defined)
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
PC
SR
Bit 0
Bit 0
INT3
Bit 31
INT3
Bit 31
LR / LR_INT3
(implementation
RAR_INT3
RSR_INT3
registers
SP_SYS
SP_SYS
INT0PC
INT1PC
FINTPC
banked
SMPC
defined)
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
PC
SR
Bit 0
Bit 0
Exception
Bit 31
Exception
Bit 31
RSR_EX
RAR_EX
SP_SYS
SP_SYS
FINTPC
FINTPC
INT0PC
INT1PC
INT0PC
INT1PC
SMPC
SMPC
R12
R11
R10
R12
R11
R10
PC
LR
SR
PC
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
Bit 0
AVR32
Figure 2-3
NMI
Bit 31
NMI
Bit 31
RSR_NMI
RAR_NMI
SP_SYS
SP_SYS
FINTPC
INT0PC
INT1PC
INT0PC
INT1PC
FINTPC
SMPC
SMPC
R12
R11
R10
R12
R11
R10
PC
SR
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Bit 0
9