AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 94

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.1.2
9.1.3
9.1.4
94
AVR32
Operator Symbols
Operations
Status Register Flags
pairs. This is also
ure to do so will
instructions.
Some instructions access or use doubleword operands. These operands must be
placed in two consecutive register addresses where the first register must be an even
register. The even register contains the least significant part and the odd register con-
tains the most significant part. This ordering is reversed in comparison with how data is
organized in memory (where the most significant part would receive the lowest address)
and is intentional.
[i:j]
The programmer is responsible for placing these operands in properly aligned register
specified in the "Operands" section in the detailed description of each instruction. Fail-
result in an undefined behaviour.
∧
∨
⊗
¬
Sat
ASR(x, n)
Bits(x)
LSR(x, n)
LSL(x, n)
SATS(x, n)
SATSU(x, n)
SATU(x, n)
SE(x, n)
SE(x)
ZE(x, n)
ZE(x)
C:
Z:
N:
V:
Q:
M0:
Denotes bit i to j in an immediate value.
Number of bits in operand x
x >> n
x << n
Identical to SE(x, 32)
Identical to ZE(x, 32)
Bitwise logical AND operation.
Bitwise logical OR operation.
Bitwise logical EOR operation.
Bitwise logical NOT operation.
Saturate operand
SE(x, Bits(x) + n) >> n
Signed Saturation ( x is treated as a signed value ):
If (x > (2
Signed to Unsigned Saturation ( x is treated as a signed value ):
If (x > (2
Unsigned Saturation ( x is treated as an unsigned value ):
If (x > (2
Sign Extend x to an n-bit value
Zero Extend x to an n-bit value
Carry / Borrow flag.
Zero flag, set if the result of the operation is zero.
Bit 31 of the result.
Set if 2’s complement overflow occurred.
Saturated flag, set if saturation and/or overflow has occurred after some
Mode bit 0
n-1
n
n
-1)) then (2
-1)) then (2
-1)) then (2
n-1
n-1
n-1
-1); elseif ( x < 0 ) then 0; else x;
-1); else x;
-1); elseif (x < -2
n-1
) then -2
n-1
; else x;
32000D–04/2011