AT32UC3C2128C Atmel Corporation, AT32UC3C2128C Datasheet - Page 103
AT32UC3C2128C
Manufacturer Part Number
AT32UC3C2128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C2128C
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2128C-A2UR
Manufacturer:
ATMEL
Quantity:
1 043
Part Number:
AT32UC3C2128C-Z2UR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
9.2.14.6
32002F–03/2010
Debug Communication Control Register (DCCR)
Table 9-9.
To enable the DCCPU read and DCEMU dirty interrupts the corresponding enable bits must be
set in this register.
Table 9-10.
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Bit Number
1
1
0
Bit Number
31:2
1
0
Debug Communication Status Register
Debug Communication Control Register
Field Name
CPURI
EMUD
CPUD
Field Name
Reserved
DCCPUIMASK
DCEMUIMASK
Init. Val.
0
0
0
Init. Val.
0x0000_
0000
0
0
Description
CPU Data Read Interrupt flag
0 = DCCPU has not been read since the clearing
of this bit.
1 = DCEMU has been read.
This bit is cleared by writing this bit to 0.
Emulator Data Dirty
0 = DCEMU has not been written to since last read
from CPU.
1 = DCEMU contains a new data value.
This bit is cleared by reading DCEMU.
CPU Data Dirty
0 = DCCPU has not been written to since last read
from emulator.
1 = DCCPU contains a new data value.
This bit is cleared by reading DCCPU.
Description
Reserved
These bits are reserved, and will always read
as 0
DCCPU Interrupt Mask
0 = DCCPU interrupts are disabled.
1 = DCCPU interrupts are enabled.
DCEMU Interrupt Mask
0 = DCEMU interrupts are disabled.
1 = DCEMU interrupts are enabled.
AVR32
103