AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 228

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

228
AVR32
MTDR – Move to Debug Register
Architecture revision:
Architecture revision1 and higher.
Description
The instruction copies the value in the specified register to the specified debug register. Note
that special timing concerns must be considered when operating on the system registers, see
the Pipeline Chapter for details.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Note:
The debug registers are implementation defined, and updates of these registers are handled in
an implementation specific way.
This instruction can only be executed in a privileged mode. Execution from any other mode will
trigger a Privilege Violation exception.
31
1
15
0
DebugRegister[DebugRegisterAddress << 2] ← Rs;
mtdr
DebugRegisterAddress ∈ {0, 4, 8, ..., 1020}
Q:
V:
N:
Z:
C:
1
0
1
0
DebugRegisterAddress, Rs
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
0
0
0
0
1
0
1
0
8
1
0
7
1
0
Debug Register Ad-
1
20
1
19
Rs
32000D–04/2011
0
16