AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 52
AT32UC3C264C
Manufacturer Part Number
AT32UC3C264C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C264C
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C264C-A2UR
Manufacturer:
INTERSIL
Quantity:
1 670
Part Number:
AT32UC3C264C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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7.6
7.6.1
Figure 7-2.
7.6.1.1
7.6.1.2
32117C–AVR-08/11
Main Clock
Sources
Functional Description
Synchronous Clocks
Selecting the main clock source
Selecting synchronous clock division ratio
Synchronous Clock Generation
MCSEL
The System RC Oscillator (RCSYS) or a set of other clock sources provide the source for the
main clock, which is the common root for the synchronous clocks for the CPU/HSB and PBx
modules. For details about the other main clock sources, please refer to the register description
of the Main Clock Control Register (MCCTRL). The main clock is divided by an 8-bit prescaler,
and each of these synchronous clocks can run from any tapping of this prescaler, or the undi-
vided main clock, as long as f
fly, responding to varying load in the application. The clock domains can be shut down in sleep
mode, as described in
nous clock domain can be individually masked, to avoid power consumption in inactive modules.
The common main clock can be connected to RCSYS or a set of other clock sources. For details
about the other main clock sources, please refer to the register description of the Main Clock
Control Register (MCCTRL). By default, the main clock will be connected to RCSYS. The user
can connect the main clock to an other source by writing the MCSEL field in the MCCTRL regis-
ter. This must only be done after that unit has been enabled and is ready, otherwise a deadlock
will occur. Care should also be taken that the new frequency of the synchronous clocks does not
exceed the maximum frequency for each clock domain.
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CPUDIV in CPUSEL register to one and CPUSEL in
CPUSEL register to the value, resulting in a CPU clock frequency:
Prescaler
f
CPU
= f
Instruction
main
Sleep
/ 2
(CPUSEL+1)
CPUSEL
Section
CPUDIV
CPU
7.6.3. Additionally, the clocks for each module in each synchro-
0
1
≥ f
Controller
Main Clock
PBx,
Sleep
. The synchronous clock source can be changed on-the
CPUMASK
Mask
AT32UC3C
CPU Clocks
HSB Clocks
PBx Clocks
52
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