AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 888
AT32UC3C264C
Manufacturer Part Number
AT32UC3C264C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C264C
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
INTERSIL
Quantity:
1 670
Part Number:
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Manufacturer:
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
- Current page: 888 of 1313
- Download datasheet (20Mb)
32.6.2.15
32117C–AVR-08/11
RXOUTI
FIFOCON
OUT
Management of OUT endpoints
• Overview
(bank 0)
DATA
set, or if the total byte count is not an integral multiple of EPSIZE, whereby the last packet
should be short.
To enable the multi packet mode, the user should configure the endpoint descriptor
(EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of the multi packet, which should be
larger than the endpoint size (EPSIZE).
Since the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE is incremented (by the transmitted
packet size) after each successful transaction, it should be set to zero when setting up a new
multi packet transfer.
The EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE is cleared by hardware when all the bank
contents have been sent. The bank is considered as ready and the TX_IN flag is set when:
The endpoint and its descriptor in RAM must be pre configured, see section
on page 881
When the current bank is full, the RXOUTI and FIFO Control (UECONn.FIFOCON) bits will be
set simultaneously. This triggers an EPnINT interrupt if the Received OUT Data Interrupt Enable
(RXOUTE) bit in UECONn is one.
RXOUTI shall be cleared by software (by writing a one to the Received OUT Data Interrupt Clear
(RXOUTIC) bit) to acknowledge the interrupt. This has no effect on the endpoint FIFO.
The user reads the OUT data from the RAM and clears the FIFOCON bit to free the bank. This
will also cause a switch to the next bank if the OUT endpoint is composed of multiple banks.
RXOUTI should always be cleared before clearing FIFOCON to avoid missing an RXOUTI
event.
Figure 32-14. Example of an OUT endpoint with one data bank
• A short packet (smaller than EPSIZE) has been transmitted.
• A packet has been successfully transmitted, the updated MULTI_PACKET_SIZE equals the
• An extra zero length packet has been automatically sent for the last transfer of the current
BYTE_COUNT, and the AUTO_ZLP field is not set.
bank, if BYTE_COUNT is a multiple of EPSIZE and AUTO_ZLP is set.
HW
ACK
for more details.
SW
read data from CPU
BANK 0
NAK
SW
OUT
(bank 0)
DATA
HW
ACK
AT32UC3C
”RAM management”
read data from CPU
SW
BANK 0
888
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