AT86RF212 Atmel Corporation, AT86RF212 Datasheet

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AT86RF212

Manufacturer Part Number
AT86RF212
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT86RF212

Max. Operating Frequency
0 MHz
Crypto Engine
AES
Operating Voltage (vcc)
1.8 to 3.6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120

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Features
• Fully Integrated 700/800/900 MHz-Band Transceiver
• Direct Sequence Spread Spectrum with Different Modulation Schemes and
• Flexible Combination of Frequency Bands and Data Rates
• Industry Leading Link Budget
• Low Power Supply Voltage from 1.8 V to 3.6 V
• Low Current Consumption
• Digital Interface
• Radio Transceiver Features
• IEEE 802.15.4-2006 Hardware Support
• Compliant to IEEE 802.15.4-2003, IEEE 802.15.4-2006, IEEE 802.15.4c-2009,
• MAC Hardware Accelerator
• AES 128 bit Hardware Accelerator (ECB and CBC modes)
• Extended Feature Set Hardware Support
• Optimized for Low BoM Cost and Ease of Production
• Industrial Temperature Range from -40 °C to +85 °C
• 32-pin Low-profile Lead-free Plastic QFN Package, 5.0 x 5.0 x 0.9 mm
- Chinese WPAN Band from 779 to 787 MHz
- European SRD Band from 863 to 870 MHz
- North American ISM Band from 902 to 928 MHz
Data Rates
- BPSK with 20 and 40 kbit/s, compliant to IEEE 802.15.4-2003/2006
- O-QPSK with 100 and 250 kbit/s, compliant to IEEE 802.15.4-2006
- O-QPSK with 250 kbit/s, compliant to IEEE 802.15.4c-2009
- O-QPSK with 200, 400, 500, and 1000 kbit/s PSDU Data Rate
- Receiver Sensitivity up to -110 dBm
- Programmable TX Output Power up to +10 dBm
- Internal Voltage Regulators and Battery Monitor
- SLEEP
- TRX_OFF = 0.4 mA
- RX_ON
- BUSY_TX = 17 mA at P
- Registers, Frame Buffer, and AES Accessible through SPI
- Clock Output with Configurable Rate
- Adjustable Receiver Sensitivity
- Integrated TX/RX Switch, LNA, and PLL Loop Filter
- Fast Settling PLL Supporting Frequency Hopping
- Automatic VCO and Filter Calibration
- Integrated 16 MHz Crystal Oscillator
- 128 byte FIFO for Transmit/Receive
- FCS Computation and Check
- Clear Channel Assessment
- Received Signal Strength Indicator, Energy Detection, and Link Quality
- Automatic Acknowledgement and Retransmission
- CSMA-CA and Listen before Talk
- Automatic Frame Filtering
- True Random Number Generation for Security Applications
- TX/RX Indication for External RF Front End Control
- Configurable SFD
- Low External Component Count: Antenna, Reference Crystal, and Bypass
- Excellent ESD Robustness
ETSI EN 300 220-1, and FCC 47 CFR Section 15.247
Indication
Capacitors
= 0.2 µA
= 9.2 mA
TX
= 5 dBm
3
Low Power
700/800/900 MHz
Transceiver for
IEEE
IEEE
Zigbee,
6LoWPAN, and
ISM Applications
AT86RF212
802.15.4
802.15.4c
8168C-MCU Wireless-02/10
-2006
-2009
,
,

Related parts for AT86RF212

AT86RF212 Summary of contents

Page 1

... Low-profile Lead-free Plastic QFN Package, 5.0 x 5.0 x 0.9 mm • Compliant to IEEE 802.15.4-2003, IEEE 802.15.4-2006, IEEE 802.15.4c-2009, ETSI EN 300 220-1, and FCC 47 CFR Section 15.247 Low Power 700/800/900 MHz Transceiver for IEEE 802.15.4 IEEE 802.15.4c Zigbee, 6LoWPAN, and ISM Applications AT86RF212 3 8168C-MCU Wireless-02/10 , -2006 , -2009 ...

Page 2

... IEEE 802.15.4c-2009 Amendment [3]. Furthermore, proprietary High Data Rate Modes up to 1000 kbit/s can be employed. The AT86RF212 is a true SPI-to-antenna solution. RF-critical components except the antenna, crystal, and de-coupling capacitors are integrated on-chip. MAC and AES hardware accelerators improve overall system power efficiency and timing. ...

Page 3

... Figure 1-1. AT86RF212 Block Diagram TX Power PA RFP RFN LNA PPF Analog Domain 8168C-MCU Wireless-02/10 Voltage XOSC Regulator Mixer LPF DAC Frequency FTN, Synthesis BATMON Mixer BPF ADC AGC AT86RF212 Configuration Registers SPI TX BBP (Slave) TRX Buffer AES RX BBP Control Logic Digital Domain ...

Page 4

... Pin Description Table 2-1. Pin Description Pin Name 1 DIG3 2 DIG4 3 AVSS 4 RFP 5 RFN 6 AVSS 7 DVSS 8 /RST 9 DIG1 AT86RF212 4 Figure 2-1. AT86RF212 Pin-out Diagram DIG3 1 exposed paddle DIG4 2 AVSS AVSS 3 RFP 4 AT86RF212 RFN 5 AVSS 6 DVSS 7 /RST Note: The exposed paddle is electrically connected to the die inside the package ...

Page 5

... Analog ground Ground Analog ground; exposed paddle of QFN package EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF212 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation. The voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio transceiver state. The voltage regulators can be configured for external supply ...

Page 6

... RF Pins AT86RF212 6 RFN, RFP A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by reducing spurious emissions originated from other digital ICs such as a microcontroller. The RF port is designed for a 100 Ω differential load path between the RF pins is allowed ...

Page 7

... Supply pin (voltage regulator output) for the analog 1.8 V voltage domain. The outputs shall be bypassed by 1 µF. The AT86RF212 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI, and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST, and DIG2). The microcontroller interface is described in detail in section 4. Additional digital output signals DIG1 … ...

Page 8

... Pull-up and Pull-down Configuration 2.2.2.3 Register Description AT86RF212 8 Pulling resistors are internally connected to all digital input pins in radio transceiver state P_ON; see section 5.1.2.1. Table 2-4 summarizes the pull-up and pull-down configuration. Table 2-4. Pull-up / Pull-Down Configuration of Digital Input Pins in P_ON State Pin /RST /SEL ...

Page 9

... Wireless-02/10 • Bit 5:4 – PAD_IO_CLKM These register bits set the output driver current of pin CLKM. Refer also to section 7.7. Table 2-7. CLKM Driver Strength Register Bits Value PAD_IO_CLKM • Bit 3:0 – CLKM_SHA_SEL, CLKM_CTRL Refer to section 7.7.6. AT86RF212 Description ...

Page 10

... F1 C2 AT86RF212 10 A basic application schematic of the AT86RF212 with a single-ended RF connector is shown in Figure 3-1. The 50 Ω single-ended RF input is transformed to the 100 Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port. Regulatory rules like FCC 47 CFR section 15 ...

Page 11

... JTI AVX Murata 1 μ AVX Murata 68 pF Epcos Epcos AVX 2.2 pF AVX Murata 680 Ω CX-4025 16 MHz ACAL Taitien SX-4025 16 MHz Siward AT86RF212 Comment 748431090 0900BL18B100 748131009 0915LP15A026 0896FB15A0100 0783FB15A0100 0603YD105KAT2A X5R GRM188R61C105KA12D (0603) 06035A120JA COG GRP1886C1H120JA01 (0603) B37930 COG B37920 ...

Page 12

... All other extended features (see section 9) do not need an extended schematic. An application schematic illustrating the use of the AT86RF212 Extended Feature Set is shown in Figure 3-2. Although this example shows all additional hardware features combined possible to use all features separately or in various combinations. ...

Page 13

... Wireless-02/10 During transmit, the AT86RF212 TX signal is amplified using an external PA (N1), low pass filtered to suppress spurious harmonics emission, and fed to the antennas via a RF switch (SW2). In this example, RF switch SW2 further supports Antenna Diversity (1) controlled by pin DIG1 . Note: 1. DIG1/DIG2 can be used as a differential pin pair to control a RF switch if RX Frame Time Stamping is not used ...

Page 14

... Figure 4-1. Microcontroller to AT86RF212 Interface Microcontrollers with a master SPI such as Atmel’s AVR family interface directly to the AT86RF212. The SPI is used for register, Frame Buffer, SRAM, and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 4-1 introduces the radio transceiver I/O signals. ...

Page 15

... All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H. /SEL = L enables the MISO output driver of the AT86RF212. The MSB of MISO is valid after t (see section 10.4, parameter 10.4.3) and is updated at each falling edge of 1 SCLK ...

Page 16

... Register Access Mode AT86RF212 16 Referring to Figure 4-2 and Figure 4-3, MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t parameters 10.4.5 and 10.4.6. ...

Page 17

... After the PSDU data, three more bytes are transferred containing the link quality indication (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of the received frame. Figure 4-7 illustrates the packet structure of a Frame Buffer read access. The structure of RX_STATUS is described in Table 4-3. AT86RF212 17 ...

Page 18

... Figure 4-8. Packet Structure - Frame Write Access Figure 4-9. Exemplary SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU AT86RF212 18 Table 4-3. RX_STATUS Bit 7 Content RX_CRC_VALID (register 0x06, PHY_RSSI) Reference Section 6.3.5 Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e ...

Page 19

... Figure 4-11. On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence; refer to Figure 4-12. Do not attempt to read or write bytes beyond the SRAM buffer size. AT86RF212 19 ...

Page 20

... Figure 4-13. Exemplary SPI Sequence – SRAM Read Access of a 5-byte Data Package Figure 4-14. Exemplary SPI Sequence – SRAM Write Access of a 5-byte Data Package 4.4 PHY Status Information AT86RF212 20 As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H. ...

Page 21

... Register Bits Value SPI_CMD_MODE • Bit 1:0 – IRQ_MASK_MODE, IRQ_POLARITY Refer to section 4.7.2. The AT86RF212 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Additional two registers contain the JEDEC manufacture ID IRQ_2_EXT_EN TX_AUTO_CRC_ON R/W R/W ...

Page 22

... Bits [15:8] are stored in register 0x1F (MAN_ID_1). The highest 16 bits of the ID are not stored in registers. Table 4-11. JEDEC Manufacturer ID – Bits [7:0] Register Bits Value MAN_ID_0 0x1F PART_NUM[7: Description AT86RF212 part number VERSION_NUM[7:0] R Description Revision MAN_ID_0[7: ...

Page 23

... MAN_ID_1 0x00 Pin 11 (SLP_TR multi-functional pin. Its function relates to the current state of the AT86RF212 and is summarized in Table 4-14. The radio transceiver states are explained in detail in section 5. In states PLL_ON and TX_ARET_ON, pin SLP_TR is used as trigger input to initiate a TX transaction. Here pin SLP_TR is sensitive on rising edge only. ...

Page 24

... TR2 RX_ON and RX_AACK_ON states For synchronous systems where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF212 supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames ...

Page 25

... IRQ_0 (PLL_LOCK) Indicates PLL lock 8168C-MCU Wireless-02/10 The AT86RF212 supports 8 interrupt requests as listed in Table 4-15. Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ, pin 24) ...

Page 26

... Register Description AT86RF212 26 The interrupt IRQ_4 has two meanings, depending on the current radio transceiver state; refer to register 0x01 (TRX_STATUS). After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt IRQ_4 (AWAKE_END) when it enters state TRX_OFF. The second meaning is only valid for receive states. If the microcontroller initiates CCA measurement, the completion of the measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE) ...

Page 27

... The pin remains at high level until the end of the frame receive procedure. For further details refer to section 9. TRX_UR AMI RX_START PLL_UNLOCK TX_AUTO_CRC_ON IRQ_2_EXT_EN R/W R SPI_CMD_MODE IRQ_MASK_MODE R/W R AT86RF212 4 CCA_ED_DONE PLL_LOCK RX_BL_CTRL R IRQ_POLARITY R ...

Page 28

... Bit 3:2 – SPI_CMD_MODE Refer to section 4.4.1. • Bit 1 – IRQ_MASK_MODE The AT86RF212 supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE. Even if an interrupt request is masked by the corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS). The different options are shown in Table 4-19. ...

Page 29

... Table 4-20. Configuration of Pin 24 (IRQ) Register Bit Value IRQ_POLARITY 0 1 This setting does not affect the polarity of the Frame Buffer Empty Indicator, refer to section 9.6. The Frame Buffer Empty Indicator is always active high. AT86RF212 Description pin IRQ high active pin IRQ low active 29 ...

Page 30

... Figure 5-1. Basic Operating Mode State Diagram (for timing refer to Table 5-1) AT86RF212 30 This section summarizes all states to provide the basic functionality of the AT86RF212, such as receiving and transmitting frames, the power up sequence, and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the corresponding radio transceiver states are shown in Figure 5-1 ...

Page 31

... All digital inputs have pull-up or pull-down resistors during P_ON state, refer to section 2.2.2.2. This is necessary to support microcontrollers where GPIO signals are floating TRX_STATE), or directly by → SLEEP → RX_ON_NOCLK → BUSY_TX → TRX_OFF → RX_ON ) is applied first to the AT86RF212, the radio DD AT86RF212 two signal pins: 31 ...

Page 32

... SLEEP – Sleep State 5.1.2.3 TRX_OFF – Clock State AT86RF212 32 after power-on or reset. The input pull-up and pull-down resistors are disabled when the radio transceiver leaves P_ON state. Leaving P_ON state, outputs pins DIG1/DIG2 are internally connected to digital ground, whereas pins DIG3/DIG4 are internally connected to analog ground, unless their configuration is changed ...

Page 33

... This specific power-down scenario – for systems running in clock synchronous mode (see section 4) – is supported by the AT86RF212 using the state RX_ON_NOCLK. This state can only be entered by setting pin 11 (SLP_TR while the radio transceiver is in RX_ON state ...

Page 34

... RX_ON state. The radio transceiver only reenters the RX_ON_NOCLK state when the next rising edge of pin SLP_TR pin occurs. If the AT86RF212 is in the RX_ON_NOCLK state and pin SLP_TR is reset to logic low, it enters the RX_ON state and it starts to supply clock on the CLKM pin again. ...

Page 35

... During reset, the microcontroller has to set the radio transceiver control pins SLP_TR and /SEL to their default values. An overview of the register reset values is provided in Table 11-2. All interrupts provided by the AT86RF212 (see Table 4-15) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. ...

Page 36

... Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END) if this interrupt was enabled by the appropriate mask register bit. The transition from TRX_OFF to PLL_ON or RX_ON state and further to RX_ON or PLL_ON is shown in Figure 5- supplied to the AT86RF212, the radio DD , the master clock signal is available TR1 , the radio transceiver enters TRX_OFF state. ...

Page 37

... TX_START. The PLL settles to the transmit frequency and the PA is enabled. After the duration symbol period), the AT86RF212 changes into BUSY_TX state, TR10 transmitting the internally generated SHR and the PSDU data of the Frame Buffer. After ...

Page 38

... TR3 4 t TRX_OFF PLL_ON TR4 AT86RF212 38 The radio transceiver reset procedure is shown in Figure 5-7. Figure 5-7. Reset Procedure /RST = L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to section 7.7.4. After releasing the reset pin (/RST = H), the wake-up sequence including an FTN calibration cycle is performed, refer to section 7 ...

Page 39

... RSSI update period in receive states, refer to section 6.4.2 BPSK-40: 24 µs O-QPSK: 8 µs 8 symbol periods ED measurement period; different timing with High Data Rate Modes, see sections 6.5.2 and 7.1.4.3 8 symbol periods CCA measurement period, refer to section 6.6.2 AT86RF212 TRX_OFF (see pF PLL_ON, including 150 µs AVREG ) ...

Page 40

... Register Description AT86RF212 40 Register 0x01 (TRX_STATUS): A read access to TRX_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, a state transition can be initiated by the rising edge of pin 11 (SLP_TR) in the appropriate state. This register is used for Basic and Extended Operating Mode, refer to section 5 ...

Page 41

... Extended Operating Mode only, refer to section 5.2. TRAC_STATUS TRAC_STATUS TRX_CMD[2] TRX_CMD[1] R/W R State Transition towards NOP TX_START FORCE_TRX_OFF FORCE_PLL_ON RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) RX_AACK_ON TX_ARET_ON All other values are reserved and mapped to NOP. AT86RF212 4 TRX_CMD[4] R TRX_CMD[0] R ...

Page 42

... Automatic retry of transmissions if ACK was expected but not received or accepted • Interrupt signaling with transaction status An AT86RF212 state diagram, including the Extended Operating Mode states, is shown in Figure 5-8. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. ...

Page 43

... Figure 5-8. Extended Operating Mode State Diagram 8168C-MCU Wireless-02/10 AT86RF212 43 ...

Page 44

... TX_START to register bits TRX_CMD. The TX_ARET Extended Operating Mode is terminated by writing the command PLL_ON to the register bits TRX_CMD. If the AT86RF212 is within a CSMA-CA, a frame-transmit or an acknowledgment procedure (BUSY_TX_ARET), the state change is executed after finish. Alternatively, the command FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into transceiver state PLL_ON ...

Page 45

... The RX_AACK Extended Operating Mode handles reception and automatic acknowledgement of IEEE 802.15.4 compliant frames. The general flow of the RX_AACK algorithm is shown in Figure 5-9. Here the gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 AT86RF212 registers 0x20 – 0x2B registers 0x2C, 0x2E register 0x17 ...

Page 46

... In that case, an interrupt IRQ_3 is issued for all frames. During reception, the AT86RF212 parses bit 5 (ACK Request) of the frame control field of the received data or MAC command frame to check if an acknowledgement (ACK) response is expected. In that case and if the frame matches the third level filtering rules (see IEEE 802 ...

Page 47

... Figure 5-9. Flow Diagram of RX_AACK 8168C-MCU Wireless-02/10 AT86RF212 47 ...

Page 48

... AT86RF212 48 RX_AACK configuration as described below shall be done prior to switching the AT86RF212 into state RX_AACK_ON, refer to section 5.2.1. Table 5-8 summarizes all register bits which affect the behavior of an RX_AACK transaction. For frame filtering it is further required to setup address registers to match to the expected address. ...

Page 49

... IEEE 802.15.4-2006 standard compliant networks. The same holds for PAN coordinators, see below. PAN Coordinator Table 5-10 shows the RX_AACK configuration registers required to setup a PAN coordinator device. AT86RF212 Description Setup Frame Filter, see section 6.2.1 0: Disable frame protection 1: Enable frame protection 0: Transceiver operates in unslotted mode ...

Page 50

... AT86RF212 50 Table 5-10. Configuration of a PAN Coordinator Register Register Name Address Bit 0x20,0x21 SHORT_ADDR_0/1 0x22,0x23 PAN_ADDR_0/1 0x24 IEEE_ADDR_0 … … 0x2B IEEE_ADDR_7 0x0C 7 RX_SAFE_MODE 0x2C 0 SLOTTED_OPERATION 0x2E 3 AACK_I_AM_COORD 0x2E 5 AACK_SET_PD 0x2E 7:6 AACK_FVN_MODE Promiscuous Mode or Sniffer The promiscuous mode is described in IEEE 802.15.4-2006, section 7.5.6.5. This mode is further illustrated in Figure 5-9 ...

Page 51

... This might be required when implementing proprietary, non- standard compliant protocols. The reception of reserved frame types is an extension of the AT86RF212 Frame Filter, see section 6.2. Received frames are either handled like data frames, or may be allowed to completely bypass the Frame Filter. The flow chart in Figure 5-9 shows the corresponding state machine ...

Page 52

... AACK_ACK_TIME If the AT86RF212 is listening for an incoming frame and the microcontroller is not running an application, the microcontroller can be powered down to decrease the total system power consumption. This special power-down scenario for systems running in clock synchronous mode (see section 4.2) is supported by the AT86RF212 using the states RX_AACK_ON_NOCLK and BUSY_RX_AACK_NOCLK, see Figure 5-8 ...

Page 53

... IEEE 802.15.4-2006, section 7.5.6.4.2. In conjunction with the microcontroller the AT86RF212 supports slotted acknowledgement operation. This mode is invoked by setting register bit SLOTTED_OPERATION (register 0x2C, XAH_CTRL_0 acknowledgment (ACK) frame transmitted in RX_AACK mode, the radio transceiver expects a rising edge on pin 11 (SLP_TR) to actually start the transmission ...

Page 54

... A general timing example of an RX_AACK transaction is shown in Figure 5-11. In this example, a data frame with an ACK request is received. The AT86RF212 changes to state BUSY_RX_AACK after SFD detection. The completion of the frame reception is indicated by a TRX_END interrupt. The interrupts IRQ_2 (TX_START) and IRQ_5 (AMI) are disabled in this example ...

Page 55

... Wireless-02/ transmission is initiated in TX_ARET mode, the AT86RF212 executes the CSMA-CA algorithm as defined by IEEE 802.15.4-2006, section 7.5.1.4. If the CCA reports IDLE, the frame is transmitted from the Frame Buffer acknowledgement frame is requested, the radio transceiver checks for an ACK reply automatically. The CSMA-CA based transmission process is repeated as long as no valid acknowledgement is received or the number of frame retransmissions (MAX_FRAME_RETRIES) is exceeded ...

Page 56

... Figure 5-12. Flow Diagram of TX_ARET AT86RF212 56 8168C-MCU Wireless-02/10 ...

Page 57

... Received frames, other than the expected ACK frame, are discarded automatically acknowledgment (ACK) frame is expected after frame transmission, the AT86RF212 sets a timeout until which a valid ACK frame must have been arrived. This timeout macAckWaitDuration is defined according to [2] as follows: macAckWaitDuration [symbol periods] = ...

Page 58

... Figure 5-13. Exemplary Timing of a TX_ARET Transaction (without Pending Data Bit set in ACK Frame) 5.2.5 Interrupt Handling AT86RF212 58 After that, the AT86RF212 switches to receive mode and expects an acknowledgement response, which is indicated by register subfield TRAC_STATUS (register 0x02, TRX_STATE) set to SUCCESS_WAIT_FOR_ACK. After a period of aTurnaroundTime + aUnitBackoff, the transmission of the ACK frame must have started. During the entire ...

Page 59

... Frame Filter configuration Short address, PAN ID, and IEEE address - See section 6.2.3 - TX_ARET control, retries value control CSMA-CA seed value CSMA-CA seed value, RX_AACK control CSMA-CA backoff exponent control 6 5 CCA_STATUS Reserved TRX_STATUS[2] TRX_STATUS[ AT86RF212 4 TRX_STATUS[ TRX_STATUS[ ...

Page 60

... Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Register 0x02 (TRX_STATE): The AT86RF212 radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. A successful state transition shall be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS). ...

Page 61

... Bit 7 Name PA_EXT_EN Read/Write R/W Reset Value 0 RX_AACK State Description NOP TX_START FORCE_TRX_OFF FORCE_PLL_ON RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) RX_AACK_ON TX_ARET_ON All other values are reserved and mapped to NOP IRQ_2_EXT_EN TX_AUTO_CRC_ON R/W R AT86RF212 TX_ARET RX_BL_CTRL R ...

Page 62

... AT86RF212 62 Bit 3 Name SPI_CMD_MODE Read/Write R/W Reset Value 0 • Bit 7 – PA_EXT_EN Refer to section 9.4.3. • Bit 6 – IRQ_2_EXT_EN Refer to section 9.5.2. • Bit 5 – TX_AUTO_CRC_ON If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For further details refer to section 6.3. • Bit 4 – RX_BL_CTRL Refer to section 9.6.2. • ...

Page 63

... AACK_DIS_ACK (register 0x2E, CSMA_SEED_1). • Bit 0 – Reserved Register 0x2C (XAH_CTRL_0): Register 0x2C (XAH_CTRL_0 control register for Extended Operating Mode. Table 5-25. Register 0x2C (XAH_CTRL_0) Bit 7 Name Read/Write Reset Value 0 ACK response time [symbol periods MAX_FRAME_RETRIES[3:0] R AT86RF212 ...

Page 64

... AT86RF212 64 Bit 3 Name MAX_CSMA_RETRIES[2:0] Read/Write Reset Value 1 • Bit 7:4 – MAX_FRAME_RETRIES The setting of MAX_FRAME_RETRIES specifies the number of attempts in TX_ARET mode to automatically retransmit a frame when it was not acknowledged by the recipient. • Bit 3:1 – MAX_CSMA_RETRIES MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the ...

Page 65

... The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement behavior of the AT86RF212. According to the content of these register bits, the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number ...

Page 66

... AT86RF212 66 • Bit 4 – AACK_DIS_ACK If this bit is set, no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode, even if requested. • Bit 3 – AACK_I_AM_COORD This register bit has to be set if the node is a PAN coordinator used for frame filtering in RX_AACK mode. If I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId ...

Page 67

... The SHR consists of a four-octet preamble field (all zero), followed by a single octet start-of-frame delimiter (SFD). During transmit, the SHR is automatically generated by the AT86RF212, thus the Frame Buffer shall contain PHR and PSDU only, see section 4.3.2. The transmission of the SHR requires 40 symbols for a transmission with BPSK modulation and 10 symbols for a transmission with O-QPSK modulation ...

Page 68

... MAC Protocol Data Unit (MPDU) Figure 6-2. IEEE 802.15.4-2006 Frame Format – MAC Layer Frame Structure 6.1.2.1 MAC Header (MHR) 6.1.2.2 Frame Control Field (FCF) AT86RF212 68 Table 6-1 shows timing information for the above mentioned frame structure depending on the selected data rate. Table 6-1. PPDU Timing ...

Page 69

... Bit 6, the “PAN ID Compression” subfield, indicates that in a frame where both the destination and source addresses are present, the PAN ID is omitted from the source addressing field. This bit is evaluated by the Frame Filter of the AT86RF212. Bits [9:7] are reserved. Bits [11:10]: The “Destination Addressing Mode” subfield describes the format of the destination address of the frame ...

Page 70

... Addressing Mode”. The addressing field description bits of the FCF (Bits 0... 10…15) affect the AT86RF212 Frame Filter, see section 6.2. All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003, with two exceptions: a coordinator realignment command frame with the Channel Page field present (see [2], section 7 ...

Page 71

... The Frame Filter in the AT86RF212 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions. The Auxiliary Security Header terminates the MHR. This field has a variable length and ...

Page 72

... Configuration AT86RF212 72 Address matching, indicated by interrupt IRQ_5 (AMI), is furthermore controlled by the FCF of a received frame according to the following rule: If Destination Addressing Mode is 0/1 and Source Addressing Mode is 0 (see section 6.1.2.2), no interrupt IRQ_5 is generated. This causes that no acknowledgement frame is announced. For backward compatibility with IEEE 802.15.4-2003, the third level filter rule 2 (Frame Version) can be disabled by register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) ...

Page 73

... If AACK_UPLD_RES_FT = 1, received frames which are identified as reserved frames will not be blocked. See section 6.2.2 for details. • Bit 3 – Reserved • Bit 2 – AACK_ACK_TIME Refer to sections 5.2.3.3 and 5.2. AACK_FLTR_RES_FT CSMA_LBT_MODE R/W R AACK_ACK_TIME AACK_PROM_MODE R/W R IEEE 802.15.4 compliant AT86RF212 4 AACK_UPLD_RES_FT R Reserved R 0 data frame ...

Page 74

... AT86RF212 74 • Bit 1 – AACK_PROM_MODE Refer to section 5.2.6. • Bit 0 – Reserved Register 0x20 (SHORT_ADDR_0): This register contains the lower 8 bit of the 16-bit short address for Frame Filter address recognition, i.e. bits [7:0]. Table 6-8. Register 0x20 (SHORT_ADDR_0) Bit 7 6 Name Read/Write Reset Value 1 1 Register 0x21 (SHORT_ADDR_1): This register contains the higher 8 bit of the 16-bit short address for Frame Filter address recognition, i ...

Page 75

... This register contains bits [31:24] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-15. Register 0x27 (IEEE_ADDR_3) Bit 7 6 Name Read/Write Reset Value 0 0 Register 0x28 (IEEE_ADDR_4): This register contains bits [39:32] of the 64-bit IEEE extended address for Frame Filter address recognition. AT86RF212 IEEE_ADDR_0[7:0] R ...

Page 76

... AT86RF212 76 Table 6-16. Register 0x28 (IEEE_ADDR_4) Bit 7 6 Name Read/Write Reset Value 0 0 Register 0x29 (IEEE_ADDR_5): This register contains bits [47:40] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-17. Register 0x29 (IEEE_ADDR_5) Bit 7 6 Name Read/Write Reset Value 0 0 Register 0x2A (IEEE_ADDR_6): This register contains bits [55:48] of the 64-bit IEEE extended address for Frame Filter address recognition ...

Page 77

... The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement behavior of the AT86RF212. According to the content of these register bits, the radio transceiver passes frames with a specific set of frame version numbers. ...

Page 78

... The automatic FCS generation is enabled with register bit TX_AUTO_CRC_ON = 1. This allows the AT86RF212 to compute the FCS autonomously. For a frame with a frame length field specified ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer and the resulting FCS octets are transmitted in place of the last two octets of the Frame Buffer ...

Page 79

... SHR detection. A value of “1” corresponds to a valid FCS; a value of “0” corresponds to an invalid FCS. • Bit 6:5 – RND_VALUE Refer to section 9.2.2. • Bit 4:0 – RSSI Refer to section 6.4. RND_VALUE[1] RND_VALUE[ RSSI[2] RSSI[ AT86RF212 4 RSSI[ RSSI[ ...

Page 80

... Received Signal Strength Indicator (RSSI) 6.4.1 Overview 6.4.2 Reading RSSI 6.4.3 Data Interpretation AT86RF212 80 The Received Signal Strength Indicator is characterized by: • a dynamic range • a resolution of about 3 dB The RSSI value indicates the received signal power in the selected channel. No attempt is made to distinguish IEEE 802.15.4 signals from others; only the received signal strength is evaluated ...

Page 81

... BPSK with 300 kchip/s BPSK with 600 kchip/s O-QPSK with 400 kchip/s O-QPSK with 1000 kchip/s (SIN) -60 -40 Receiver Input Power [dBm RND_VALUE[1] RND_VALUE[ RSSI[2] RSSI[ AT86RF212 - RSSI[ RSSI[ ...

Page 82

... Energy Detection (ED) 6.5.1 Overview 6.5.2 Measurement Description AT86RF212 82 The Energy Detection (ED) module is characterized by: • a dynamic range • a resolution of about 1 dB • a measurement time of 8 symbol periods for IEEE 802.15.4 compliant data rates The receiver ED measurement (ED scan procedure) can be used as a part of a channel selection algorithm ...

Page 83

... Interrupt Handling 6.5.5 Register Description 8168C-MCU Wireless-02/10 The PHY_ED_LEVEL (ED 8-bit register. The ED value of the AT86RF212 has a valid range from 0x00 to 0x54 (0 to 84) with a resolution of about 1 dB. Values 0x55 to 0xFE do not occur and a value of 0xFF indicates the reset value value of 0 indicates a receiver input power less than or equal to RSSI_BASE_VAL [dBm] (refer to Table 6-25) ...

Page 84

... The CCA modes are configurable via register 0x08 (PHY_CC_CCA). When being in Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA) if the AT86RF212 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS). ...

Page 85

... AT86RF212 reports a busy channel upon detection of a PHY mode specific IEEE 802.15.4 signal above RSSI_BASE_VAL [dBm] (see Table 6-25). The AT86RF212 is also capable of detecting signals below this value, but the detection probability decreases with decreasing signal power almost zero at the radio transceivers sensitivity level (see parameter 10 ...

Page 86

... Register Description AT86RF212 86 Table 6-29. CCA Measurement Period and Access in BUSY_RX State CCA Mode Request within ED Measurement 1 Energy above threshold CCA result is available after finishing automated ED measurement period. 2 Carrier sense only CCA result is immediately available after request. 3 Carrier sense with energy above threshold (AND) CCA result is available after finishing automated ED measurement period ...

Page 87

... AND “energy above threshold” Description CCA calculation not finished CCA calculation finished Description Channel indicated as busy Channel indicated as idle 6 5 CCA_MODE[1] CCA_MODE[0] R/W R CHANNEL[2] CHANNEL[1] R/W R after requesting a CCA AT86RF212 4 CHANNEL[4] R CHANNEL[0] R/W 1 measurement with 87 ...

Page 88

... CCA_ED_THRES) [dBm]. CCA modes 0 and 3 are logically related to this result. Equipment using the AT86RF212 shall conform to the established regulations. With respect to the regulations in Europe, CSMA-CA based transmission according to IEEE 802.15.4 is not appropriate. In principle, transmission is subject to low duty cycles (0 ...

Page 89

... According to [5], the maximum LBT threshold for an IEEE 802.15.4 signal is presumably -82 dBm, assuming a channel spacing of 1 MHz. The AT86RF212 supports the previously described LBT specific listening mode when operating in the Extended Operating Mode. In particular, during TX_ARET (see section 5.2.4), the CSMA-CA algorithm can be ...

Page 90

... AT86RF212 90 Register 0x09 (CCA_THRES): This register is relevant for the ED threshold when using LBT. Table 6-37. Register 0x09 (CCA_THRES) Bit 7 Name Reserved Read/Write R/W Reset Value 0 Bit 3 Name CCA_ED_THRES Read/Write R/W Reset Value 0 • Bit 7:4 – Reserved • Bit 3:0 – CCA_ED_THRES For CCA_MODE = 1, a busy channel is indicated if the measured received power is above (RSSI_BASE_VAL + 2.07 ⋅ ...

Page 91

... LQI values in between should be uniformly distributed between these two limits. During symbol detection within frame reception, the AT86RF212 uses correlation results of multiple symbols in order to compute an estimate of the LQI value. This is motivated by the fact that the mean value of the correlation result is inversely related to the probability of a detection error ...

Page 92

... For optional data rates according to IEEE 802.15.4-2006, offset quadrature phase-shift keying (O-QPSK) is supported by the AT86RF212 with a fixed chip rate of either 400 kchip/s or 1000 kchip/ chip rate of 400 kchip/s, pulse shaping is always a combination of both, half-sine shaping (SIN) and raised cosine filtering with roll-off factor 0 ...

Page 93

... Support of Basic and Extended Operating Mode • Reduced ACK timing (optional) The AT86RF212 supports alternative data rates of {200, 400, 500, 1000} kbit/s for applications not necessarily targeting IEEE 802.15.4 compliant networks. The High Data Rate Modes utilize the same RF channel bandwidth as the IEEE 802 ...

Page 94

... This can be adjusted by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level set, the AT86RF212 does not synchronize to frames with an RSSI level below that threshold. Refer to section 7.2.3 for a configuration of the sensitivity threshold with register 0x15 (RX_SYN) ...

Page 95

... Since signals of the High Data Rate Modes are not compliant to IEEE 802.15.4-2006 not supported when the AT86RF212 is operating in these modes. However, “energy above threshold” is supported. Link Quality Indicator (LQI) For the High Data Rate Modes, the link quality value does not contain useful information and should be discarded ...

Page 96

... This mode is particularly suitable for the Chinese 780 MHz band, refer to IEEE 802.15.4c-2009. Note that during reception, this bit is not evaluated within the AT86RF212 not explicitly required to align different transceivers with OQPSK_SUB1_RC_EN in order to assure interoperability ...

Page 97

... In Table 7-5 all PHY modes supported by the AT86RF212 are summarized with the relevant setting for each bit of register TRX_CTRL_2. The “-“ (minus) character means that the bit entry is not relevant for the particular PHY mode. Table 7-5. Register 0x0C (TRX_CTRL_2) Bit Alignment ...

Page 98

... Some information is also available through register access, e.g. ED value (register 0x07, PHY_ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI). The Extended Operating Mode of the AT86RF212 supports frame filtering and pending data indication. The frame receive procedure, including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer, is described in section 8 ...

Page 99

... An ongoing frame reception is not affected RF_MC[2] RF_MC[1] R/W R Reserved Reserved R/W R Each step increases the Capacitance at RF Pins [fF 108 … 540 6 5 Reserved Reserved RX_PDT_LEVEL[2] RX_PDT_LEVEL[1] R/W R AT86RF212 4 RF_MC[0] R Reserved R Reserved RX_PDT_LEVEL[0] R ...

Page 100

... The frame transmit procedure, including writing PSDU data into the Frame Buffer and initiating a transmission, is described in section 8.2. The AT86RF212 can be operated in different frequency bands, using different power levels, modulation schemes, chip rates, and pulse shaping filters. The occupied bandwidth of the transmit signal depends on the chosen mode of operation. Values ...

Page 101

... OQPSK-RC-250 1200 Figure 7-4 to Figure 7-8 show power spectra for different modes listed in Table 7-9. The spectra were captured using default settings of AT86RF212. The resolution bandwidth of the spectrum analyzer was set to 30 kHz; the video bandwidth was set to 10 kHz. Figure 7-4. Spectrum of BPSK-20 ...

Page 102

... AT86RF212 102 Figure 7-5. Spectrum of BPSK-40 0 -10 -20 -30 -40 -50 -60 -70 912 913 Figure 7-6. Spectrum of OQPSK-SIN-RC-100 914 915 Frequency [MHz] 916 8168C-MCU Wireless-02/10 ...

Page 103

... Wireless-02/10 Figure 7-7. Spectrum of OQPSK-SIN-250 Figure 7-8. Spectrum of OQPSK-RC-250 0 -10 -20 -30 -40 -50 -60 -70 910 912 AT86RF212 914 916 Frequency [MHz] 918 103 ...

Page 104

... AT86RF212 104 Figure 7-4 to Figure 7-8 illustrate typical spectra of the transmitted signals of the AT86RF212 and do not claim any limits. Refer to the local authority bodies (FCC, ETSI, etc.) for further details about definition of power spectral density masks, definition of spurious emission, allowed modulation bandwidth, transmit power, and its limits. ...

Page 105

... Table 7-12. TX Power Offset Register Bits Value GC_TX_OFFS Register 0x05 (PHY_TX_PWR): This register controls the transmitter output power PA_LT[0] Reserved R/W R Reserved GC_TX_OFFS[ Enable Lead Time [μ Power Offset [dB AT86RF212 4 Reserved R GC_TX_OFFS[0] R/W 1 105 ...

Page 106

... AT86RF212 106 Table 7-13. Register 0x05 (PHY_TX_PWR) Bit 7 Name PA_BOOST Read/Write R/W Reset Value 0 Bit 3 Name TX_PWR[3] Read/Write R/W Reset Value 0 • Bit 7 – PA_BOOST This bit enables the PA boost mode where the TX output power is increased by approximately 5 dB when PA_BOOST = boost mode, the PA linearity is decreased compared to the normal mode when PA_BOOST = 0 ...

Page 107

... AT86RF212 780 MHz Chinese Band PHY Modes: OQPSK-RC- {250,500,1000} 0xe4 Note 6 0xe5 0xe6 0xe8 Note 7 0xe9 0xea 0xca 0xaa 0xab 0xac 0x46 ...

Page 108

... AT86RF212 108 Note 6: Power settings can be used with OQPSK-RC-{250,500}. Spectral side lobes remain < -36 dBm / 100 kHz measured with a RMS detector outside F Note 7: Power settings can be used with OQPSK-RC-{250,500,1000}. Spectral side lobes remain < -36 dBm / 100 kHz measured with a RMS detector outside F Values of Table 7-15 are based on a mode dependent setting of GC_TX_OFFS (register 0x16, RF_CTRL_0) which is shown in Table 7-16 ...

Page 109

... Manufactures must take the responsibility to check measurement results against the latest regulations of nations into which they market. The AT86RF212 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other one to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible ...

Page 110

... A radio transceiver state change, except a transition to SLEEP state or a reset, does not affect the Frame Buffer content. If the radio transceiver is taken into SLEEP, the Frame Buffer is powered off and the stored data get lost. The AT86RF212 supports an IEEE 802.15.4 compliant frame format as shown in Figure 7-11. Note: 1 ...

Page 111

... Low dropout (LDO) voltage regulator • Configurable for usage of an external voltage regulator The internal voltage regulators supply a stabilized voltage to the AT86RF212. The AVREG provides the regulated 1.8 V supply voltage for the analog domain and the DVREG supplies the 1.8 V supply voltage for the digital domain. ...

Page 112

... The block “Low power voltage regulator” within the “Digital voltage regulator” maintains the DVDD supply voltage when the voltage regulator is disabled, which is the case during sleep mode. The DVDD voltage drops down to 1.5 V (typical) if the AT86RF212 is in sleep mode; all configuration register values are stored. ...

Page 113

... When turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF212. The status bits AVDD_OK = 1 and DVDD_OK = 1 of register 0x10 (VREG_CTRL) indicate an enabled and stable internal supply voltage. Reading value 0 indicates a disabled voltage regulator or the internal supply voltage is not settled to the final value ...

Page 114

... AT86RF212 114 • Bit 3 – DVREG_EXT If set, this register bit disables the internal digital voltage regulator to apply an external regulated 1.8 V supply for the digital building blocks. Table 7-20. Regulated Voltage Supply Control for Digital Building Blocks Register Bit Value DVREG_EXT 0 1 • Bit 2 – DVDD_OK This register bit indicates if the internal 1 ...

Page 115

... Note, the battery monitor is inactive during P_ON and SLEEP states, see status register 0x01 (TRX_STATUS). A supply voltage drop below the configured threshold value is indicated by interrupt IRQ_7 (BAT_LOW), see section 4.7. Note that the interrupt is issued only if BATMON_OK changes from interrupt is generated when AT86RF212 115 ...

Page 116

... Register Description AT86RF212 116 • the supply voltage is below the default 1.8 V threshold at power up (BATMON_OK was never 1), or • a new threshold is set which is still above the current supply voltage (BATMON_OK remains 0). When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. To avoid this, • ...

Page 117

... Configurable trimming capacitance array • Configurable clock output (CLKM) The crystal oscillator generates the reference frequency for the AT86RF212. All other internally generated frequencies of the radio transceiver are derived from this frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency ...

Page 118

... On the other hand, a larger crystal load capacitance results in a longer start- up time and a higher steady state current consumption PCB XTAL2 PCB AT86RF212 C TRIM XTAL_TRIM[3:0] are available. Values in the range from TRIM represents the pin input capacitance defined in Table + C ...

Page 119

... For example, if the CLKM clock rate is configured to 16 MHz, the CLKM clock rate remains at 16 MHz after a reset, however, the register bits CLKM_CTRL are set back to 1. Since CLKM_SHA_SEL reset value is 1, the CLKM clock rate changes to 1 MHz after the next SLEEP cycle if the CLKM_CTRL setting is not updated. AT86RF212 119 ...

Page 120

... Register Description AT86RF212 120 AT86RF212 provides receiver sensitivities up to -110 dBm. Detection of such small RF signals requires very clean scenarios with respect to noise and interference. Harmonics of digital signals may degrade the performance if they interfere with the wanted RF signal. A small clock jitter of digital signals can spread harmonics over a wider frequency range, thus reducing the power of certain spectral lines ...

Page 121

... No clock at pin 17 (CLKM); pin set to logic low 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 250 kHz IEEE 802.15.4 symbol rate frequencies (1) BPSK_OQPSK SUB_MODE XTAL_MODE[2] XTAL_MODE[1] R/W R XTAL_TRIM[2] XTAL_TRIM[1] R/W R AT86RF212 (1) Frequency 20 kHz 40 kHz 25 kHz 62.5 kHz 4 XTAL_MODE[0] R XTAL_TRIM[0] R/W 0 121 ...

Page 122

... AT86RF212 122 Table 7-32. Crystal Oscillator Operating Mode Register Bits Value XTAL_MODE 0x4 0xF Other • Bit 3:0 – XTAL_TRIM The register bits XTAL_TRIM control the two internal capacitance arrays connected to pins XTAL1 and XTAL2. A capacitance value in the range from 4 selectable with a resolution of 0.3 pF. ...

Page 123

... Two PLL interrupts for status indication • Fast PLL settling to support frequency hopping The PLL generates the RF frequencies for the AT86RF212. During receive and transmit operations, the frequency synthesizer operates as a local oscillator. The frequency synthesizer is implemented as a fractional-N PLL with analog compensation of the fractional phase error ...

Page 124

... PLL Settling Time and Frequency Agility 7.8.4 Calibration Loops AT86RF212 124 When the PLL is enabled during state transition from TRX_OFF to PLL_ON or RX_ON, the settling time is typically t = 200 µs (50 µs plus 150 µs settling time of the analog TR4 voltage regulator AVREG), including PLL self calibration. For more information, refer to Table 5-1 and section 7 ...

Page 125

... CC_BAND (register 0x14, CC_CTRL_1 order to enable the above described channel selection, see Table 7-35. Table 7-36. Register 0x08 (PHY_CC_CCA) Bit 7 Name CCA_REQUEST Read/Write W Reset Value 0 Bit 3 Name CHANNEL[3] Read/Write R/W Reset Value 0 • Bit 7:5 Refer to section 6.6. CCA_MODE CCA_MODE R/W R CHANNEL[2] CHANNEL[1] R/W R AT86RF212 4 CHANNEL[4] R CHANNEL[0] R/W 1 125 ...

Page 126

... AT86RF212 126 • Bit 4:0 - CHANNEL Table 7-37. Channel Assignment according to IEEE 802.15.4-2003/2006, Channel Page 0 Register Bits Value CHANNEL 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B … 0x1F Register 0x13 (CC_CTRL_0): This register controls the center frequency if the selection by channel number according to IEEE 802 ...

Page 127

... PLL_DCU_START is set to 0. The register bit is cleared immediately after finishing the calibration. • Bit 6:0 – Reserved 6 5 Reserved Reserved R/W R PLL_CF[2] PLL_CF[1] R/W R Reserved Reserved R/W R Reserved Reserved R/W R AT86RF212 4 PLL_CF[4] R PLL_CF[0] R Reserved R Reserved R/W 0 127 ...

Page 128

... Automatic Filter Tuning (FTN) 7.9.1 Overview 7.9.2 Register Description AT86RF212 128 Register 0x11 (BATMON): The MSB of this register indicates the lock status of the PLL. Table 7-42. Register 0x11 (BATMON) Bit 7 Name PLL_LOCK_CP Read/Write R Reset Value 0 Bit 3 Name BATMON_VTH[3] Read/Write R/W Reset Value 0 • Bit 7 – PLL_LOCK_CP This register bit can be used to read out the lock status of the PLL ...

Page 129

... FTN_START = 1 initiates the filter tuning calibration loop. Ones the calibration cycle has finished within a maximum time period of 25 µs, the register bit is automatically reset to 0. • Bit 6:0 – Reserved 6 5 Reserved Reserved R/W R Reserved Reserved R/W R AT86RF212 4 Reserved R Reserved R/W 0 129 ...

Page 130

... For non-time-critical operations recommended to wait for interrupt IRQ_3 (TRX_END) before starting a Frame Buffer read access. Figure 8-1 illustrates the frame receive procedure using IRQ_3 (TRX_END). Figure 8-1. Transactions between AT86RF212 and Microcontroller during Receive IRQ issued (IRQ_2) Read IRQ status, pin 24 (IRQ) deasserted ...

Page 131

... TX_START to register 0x02 (TRX_STATE) while the radio transceiver is in state PLL_ON or TX_ARET_ON. The completion of the transaction is indicated by interrupt IRQ_3 (TRX_END). Figure 8-2. Transaction between AT86RF212 and Microcontroller during Transmit Write frame data (Frame Buffer access) Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR) ...

Page 132

... The security module is based on an AES-128 core according to FIPS197 standard, refer to [9]. The security module is independent from other building blocks of the AT86RF212. Encryption and decryption can be performed in parallel to a frame transmission or reception. Controlling of the security block is implemented as an SRAM access to address space 0x82 to 0x94 ...

Page 133

... Note • ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The AT86RF212 provides this functionality as an additional feature. ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) set up the ECB mode ...

Page 134

... Figure 9-1. ECB Programming SPI Sequence – Encryption AT86RF212 134 sequence. Register AES_CTRL_MIRROR is a mirrored version of register 0x83 (AES_CTRL). In summary, the following steps are required to perform a security operation using only one SPI access: 1. Configure SPI access 2. Configure AES operation 3. Write 128-bit data block 4 ...

Page 135

... XORed with the previous cipher text data, see Figure 9-4. According to IEEE 802.15.4, the input for the very first CBC operation has to be prepared by XORing a plaintext with an initialization vector (IV). The value of the AT86RF212 135 ...

Page 136

... SPI interface. To reduce the overall processing time, the AT86RF212 provides a Fast SRAM access for the address space 0x83 to 0x94. The Fast SRAM access allows writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run) ...

Page 137

... Security module control, AES mode Depends on AES_MODE setting: AES_MODE = 1: - Contains AES_KEY (key) AES_MODE = Contains AES_STATE (128 bit data block) Mirror of register 0x83 (AES_CTRL) Reserved 6 5 Reserved Reserved Reserved Reserved AT86RF212 4 Reserved AES_DONE R 0 137 ...

Page 138

... AT86RF212 138 Table 9-4. AES Core Operation Status Register Bit Value AES_ER 0 1 • Bit 6:1 – Reserved • Bit 0 – AES_DONE Table 9-5. AES Core Operation Status Register Bit Value AES_DONE 0 1 Register 0x83 (AES_CTRL): This register controls the operation of the security module. A read or write access during AES operation terminates the current processing ...

Page 139

... This register could be used to start a security operation within a single SRAM access by appending it to the data stream and setting register bit AES_REQUEST = 1. The AT86RF212 provides a 2-bit random number generator. This random number can be used to • generate random seeds for CSMA-CA algorithm, see section 5.2 • ...

Page 140

... RF signal path. To ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each other. The AT86RF212 supports software controlled antenna diversity, i.e. the microcontroller controls which antenna is used for transmission and reception. This is done by register settings. ...

Page 141

... Figure 3-2. If the register bit is set, the control pins DIG1/DIG2 are activated in all radio transceiver states as long as register bit ANT_EXT_SW_EN is set. If the AT86RF212 is not in a receive or transmit state recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state ...

Page 142

... If the radio transceiver starts to transmit, the two pins change the polarity. This differential pin pair can be used to control PA, LNA, and RF switches. If the AT86RF212 is not in a receive or transmit state recommended to disable register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to reduce the power consumption or avoid leakage current of external RF switches and other building blocks, especially during SLEEP state ...

Page 143

... Reset Value 0 Bit 3 Name SPI_CMD_MODE Read/Write R/W Reset Value 0 • Bit 7 – PA_EXT_EN This register bit enables pin 1 (DIG3) and pin 2 (DIG4) to indicate the transmit state of the radio transceiver TX_AUTO_CRC_ON IRQ_2_EXT_EN R/W R SPI_CMD_MODE IRQ_MASK_MODE R/W R AT86RF212 4 RX_BL_CTRL R IRQ_POLARITY R/W 0 143 ...

Page 144

... RX Frame Time Stamping 9.5.1 Overview AT86RF212 144 Table 9-15. RF Front-End Control Pins PA_EXT_EN State Pin 0 n/a DIG3 DIG4 (1) 1 BUSY_TX DIG3 DIG4 Other DIG3 DIG4 Note recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP state. ...

Page 145

... Figure 9-8. • Bit 5 – TX_AUTO_CRC_ON Refer to section 6.3.5. • Bit 4 – RX_BL_CTRL Refer to section 9.6.2. • Bit 3:2 – SPI_CMD_MODE Refer to section 4.4.1. • Bit 1:0 – IRQ_MASK_MODE, IRQ_POLARITY Refer to section 4.7. TX_AUTO_CRC_ON IRQ_2_EXT_EN R/W R SPI_CMD_MODE IRQ_MASK_MODE R/W R AT86RF212 4 RX_BL_CTRL R IRQ_POLARITY R/W 0 145 ...

Page 146

... Frame Buffer Empty Indicator 9.6.1 Overview Figure 9-9. Timing Diagram of Frame Buffer Empty Indicator 9.6.2 Register Description AT86RF212 146 For time critical applications, it may be desirable to read the frame data as early as possible. To accomplish this, the Frame Buffer empty status can be indicated to the microcontroller through a dedicated pin. ...

Page 147

... Refer to section 4.4.1. • Bit 1:0 Refer to section 4.7.2. The AT86RF212 continues the reception of incoming frames as long any receive state. When a frame is successfully received and stored in the Frame Buffer, the following frame overwrites the Frame Buffer content again. To relax the timing requirements of a Frame Buffer read access, Dynamic Frame Buffer Protection prevents that a new incoming frame overwrites the Frame Buffer as long as the Frame Buffer read access has not been completed by /SEL = H, refer to section 4 ...

Page 148

... Register Description 9.8 Configurable Start-Of-Frame Delimiter (SFD) 9.8.1 Overview AT86RF212 148 The Dynamic Frame Buffer Protection is enabled if register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) is set and the transceiver state is RX_ON or RX_AACK_ON. Note that Dynamic Frame Buffer Protection only prevents write accesses from the air interface and not from the SPI interface ...

Page 149

... For IEEE 802.15.4 compliant networks, set SFD_VALUE = 0xA7 as specified in [2]. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks, the SFD value can be changed to any other value. If enabled, IRQ_2 (RX_START) is issued only if the received SFD matches SFD_VALUE and a valid PHR is received. AT86RF212 ...

Page 150

... OH 10.3.4 V Low level output voltage OL AT86RF212 150 Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied ...

Page 151

... SPI read/write, standard SRAM and frame access modes Fast SRAM read/write access mode, refer to section 9.1.5 ≥ 10 clock cycles at 16 MHz ≥ 10 clock cycles at 16 MHz Programmable via register 0x03 (TRX_CTRL_0) Relative to the event to be indicated AT86RF212 = 3 Min. Typ. (7) 25 (7) 10 ...

Page 152

... Crystal oscillator frequency CLK 10.5.6 Reference oscillator accuracy 10.5.7 Battery monitor threshold deviation AT86RF212 152 Notes: 1. Maximum pulse width less than (TX frame length + 16 µs) 2. All modes 3. Only in BPSK mode with f 4. Only in BPSK mode with f 5. Only in O-QPSK mode with f 6. Only in O-QPSK mode with f 7 ...

Page 153

... MHz, -2 dBm 782 MHz, 8 dBm 782 MHz, -2 dBm 914 MHz, 10 dBm 914 MHz, -2 dBm 868.3 MHz, 5 dBm 868.3 MHz, -2 dBm 782 MHz, 8 dBm 782 MHz, -2 dBm Except harmonics 100 kHz RBW 1 MHz RBW AT86RF212 = 3.0 V Min. Typ ...

Page 154

... Alternate channel rejection (1)(2) BPSK-40 |∆ MHz 10.7.10 Adjacent channel rejection OQPSK-SIN-250 |∆ MHz 10.7.11 Alternate channel rejection OQPSK-SIN-250 |∆ MHz AT86RF212 154 Test Conditions ° Condition AWGN channel, PER ≤ 1% (1)(2) PSDU length of 20 octets (1)(2) PSDU length of 20 octets (2) PSDU length of 20 octets ...

Page 155

... Highest sensitivity (RX_PDT_LEVEL = 0) Reduced sensitivity (RX_PDT_LEVEL > 0) Min. Typ MHz with -71 c -12 25 -100 -13 = 3.0 V, CLKM = OFF Min. Typ 9.2 8.7 4.7 0.4 0.2 AT86RF212 Max. Units dB dB dBm -57 dBm -47 dBm dBm dBm dBm dBm ±6 dB Max. Units μA 155 ...

Page 156

... Crystal Parameter Requirements No. Symbol Parameter 10.9.1 f Crystal frequency 0 10.9.2 C Load capacitance L 10.9.3 C Crystal shunt capacitance 0 10.9.4 ESR Equivalent series resistance AT86RF212 156 Condition Min. Typ. Max. Units 16 MHz 100 Ω 8168C-MCU Wireless-02/10 ...

Page 157

... SHORT_ADDR_1 0x21 8168C-MCU Wireless-02/10 The AT86RF212 provides a register space of 64 8-bit registers used to configure, control, and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value ...

Page 158

... IEEE_ADDR_3 0x28 IEEE_ADDR_4 0x29 IEEE_ADDR_5 0x2A IEEE_ADDR_6 0x2B IEEE_ADDR_7 0x2C XAH_CTRL_0 0x2D CSMA_SEED_0 0x2E CSMA_SEED_1 AACK_FVN_MODE[1:0] 0x2F CSMA_BE …. AT86RF212 158 Bit 6 Bit 5 Bit 4 PAN_ID_0[7:0] PAN_ID_1[7:0] IEEE_ADDR_0[7:0] IEEE_ADDR_1[7:0] IEEE_ADDR_2[7:0] IEEE_ADDR_3[7:0] IEEE_ADDR_4[7:0] IEEE_ADDR_5[7:0] IEEE_ADDR_6[7:0] IEEE_ADDR_7[7:0] MAX_FRAME_RETRIES[3:0] CSMA_SEED_0[7:0] AACK_SET_PD AACK_DIS_ACK MAX_BE[3:0] Bit 3 ...

Page 159

... Wireless-02/10 Power-on reset values of the AT86RF212 registers in state P_ON are shown in Table 11-2. After a reset procedure (/RST = L as described in section 5.1.4.5), the reset values of selected registers (e.g. registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 11-2. Address Reset Value ...

Page 160

... Abbreviations AT86RF212 160 ACK — Acknowledgement ADC — Analog-to-Digital Converter AES — Advanced Encryption Standard AGC — Automatic Gain Control AVREG — Analog Voltage Regulator AWGN — Additive White Gaussian Noise BATMON — Battery Monitor BBP — Base-Band Processor BPF — ...

Page 161

... Serial Peripheral Interface SRAM — Static Random Access Memory SRD — Short Range Device TRX — Transceiver TX — Transmitter VBW — Video Bandwidth VCO — Voltage Controlled Oscillator WPAN — Wireless Personal Area Network XOSC — Crystal Oscillator XTAL — Crystal AT86RF212 161 ...

Page 162

... AT86RF212-ZU Tray AT86RF212-ZUR Tape & Reel Package Type Description QN 32QN2, 32-lead 5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn 14 Soldering Information 15 Package Thermal Properties AT86RF212 162 Package Voltage Range Temperature Range QN 1.8 V – 3.6 V Industrial (-40 °C to +85 °C) Lead-free/Halogen-free QN 1.8 V – 3.6 V Industrial (-40 ° ...

Page 163

... Package Drawing – 32QN2 8168C-MCU Wireless-02/10 AT86RF212 163 ...

Page 164

... A.1 – Overview A.2 – Configuration AT86RF212 164 The AT86RF212 offers a Continuous Transmission Test Mode to support application / production tests as well as certification tests. Using this test mode, the radio transceiver transmits continuously a previously transferred frame (PRBS mode continuous wave signal (CW mode mode, one of four different signal frequencies per channel can be transmitted: • ...

Page 165

... Enable Continuous Transmission Test Mode – step # 3 W 0x09 Enable PLL_ON state R 0x01 Wait for IRQ_0 (PLL_LOCK) W 0x02 Initiate transmission, enter BUSY_TX state Perform measurement Disable Continuous Transmission Test W 0x00 Mode Reset AT86RF212 ± 0.1 MHz ± 0.25 MHz - 0.1 MHz + 0.1 MHz - 0.25 MHz + 0.25 MHz 165 ...

Page 166

... Appendix B – Errata AT86RF212 Rev. A AT86RF212 166 1. Power-on Reset It can not be guaranteed that power-on reset (as described in section 5.1.2.1) is working under all circumstances. Problem Fix / Workaround The following programming sequence should be executed after power-on to completely reset the transceiver. Please note that the microcontroller can not count on CLKM before finalization of step 5, refer to Table A-5 ...

Page 167

... NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 TM -2003: Wireless Medium Access Control (MAC) and TM -2006: Wireless Medium Access Control (MAC) and TM -2009: Wireless Medium Access Control (MAC) and AT86RF212 167 ...

Page 168

... Data Sheet Revision History Rev. 8168C-MCU Wireless-02/10 Rev. 8168B-MCU Wireless-02/09 Rev. 8168A-AVR-06/08 AT86RF212 168 Please note that the referring page numbers in this section are referring to this document. Revisions in this section are referring to the document revisions. 1. Updated Table 5-1on page 38 and Table 5-2 on page 39. ...

Page 169

... Received Signal Strength Indicator (RSSI) .......................................................... 80 6.5 Energy Detection (ED) ......................................................................................... 82 6.6 Clear Channel Assessment (CCA)....................................................................... 84 6.7 Listen Before Talk (LBT) ...................................................................................... 88 6.8 Link Quality Indication (LQI) ................................................................................. 91 7 Module Description........................................................................... 92 7.1 Physical Layer Modes .......................................................................................... 92 7.2 Receiver (RX) ....................................................................................................... 97 7.3 Transmitter (TX) ................................................................................................. 100 7.4 Frame Buffer....................................................................................................... 109 7.5 Voltage Regulators (AVREG, DVREG).............................................................. 111 7.6 Battery Monitor (BATMON) ................................................................................ 115 AT86RF212 169 ...

Page 170

... Register Reference ....................................................................... 157 12 Abbreviations ................................................................................ 160 13 Ordering Information .................................................................... 162 14 Soldering Information................................................................... 162 15 Package Thermal Properties........................................................ 162 16 Package Drawing – 32QN2 ........................................................... 163 Appendix A – Continuous Transmission Test Mode ...................... 164 A.1 – Overview ......................................................................................................... 164 A.2 – Configuration................................................................................................... 164 Appendix B – Errata........................................................................... 166 AT86RF212 Rev. A .................................................................................................. 166 8168C-MCU Wireless-02/10 ...

Page 171

... Wireless-02/10 References.......................................................................................... 167 Data Sheet Revision History ............................................................. 168 Rev. 8168C-MCU Wireless-01/10 ............................................................................ 168 Rev. 8168B-MCU Wireless-02/09 ............................................................................ 168 Rev. 8168A-AVR-06/08............................................................................................ 168 Table of Contents............................................................................... 169 AT86RF212 171 ...

Page 172

... Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Europe ...

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