AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 104

• Manufacturer Part Number: AT89C5130A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5130A-M

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

20.1
104
Description
AT89C5130A/31A-M
The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the
Synchronous Serial Control register (SSCON;
ter (SSDAT;
12) and the Synchronous Serial Address register (SSADR
SSCON is used to enable the TWI interface, to program the bit rate (see
slave modes, to acknowledge or not a received data, to send a START or a STOP condition on
the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI
module.
SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus.
The three least significant bits are always zero. The five most significant bits contains the status
code. There are 26 possible status codes. When SSCS contains F8h, no relevant state informa-
tion is available and no serial interrupt is requested. A valid status code is available in SSCS one
machine cycle after SI is set by hardware and is still present one machine cycle after SI has
been reset by software. to Table 20-9. give the status for the master modes and miscellaneous
states.
SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It
is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a
defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is
set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always
contains the last byte present on the bus.
SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI
module will respond when programmed as a slave transmitter or receiver. The LSB is used to
enable general call address (00h) recognition.
Figure 20-3
Figure 20-3. Complete Data Transfer on 2-wire Bus
The four operating modes are:
Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to
Figure 20-7.. These figures contain the following abbreviations:
S
• Master Transmitter
• Master Receiver
• Slave transmitter
• Slave receiver
: START condition
SDA
SCL
shows how a data transfer is accomplished on the 2-wire bus.
Table
start
condition
S
20-11), the Synchronous Serial Control and Status register (SSCS;
MSB
1
2
7
8
signal from receiver
acknowledgement
ACK
Table
9
20-10), the Synchronous Serial Data regis-
while interrupts are serviced
clock line held low
1
Table
2
20-13).
3-8
ACK
signal from receiver
9
acknowledgement
Table
20-3), to enable
4337K–USB–04/08
condition
stop
Table 20-
P