AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 106

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AT89C5130A-M

Manufacturer Part Number
AT89C5130A-M
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT89C5130A-M

Flash (kbytes)
16 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART/USB
Watchdog
Yes
20.1.3
106
AT89C5130A/31A-M
Slave Receiver Mode
address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared
before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowledgement
bit has been received, the serial interrupt flag is set again and a number of status code in SSCS
are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the
slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these sta-
tus code is detailed in Table . This scheme is repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table 7 to
Table 11. After a repeated START condition (state 10h) the TWI module may switch to the mas-
ter transmitter mode by loading SSDAT with SLA+W.
In the slave receiver mode, a number of data bytes are received from a master transmitter
(Figure 20-6). To initiate the slave receiver mode, SSADR and SSCON must be loaded as
follows:
Table 20-2.
The upper 7 bits are the address to which the TWI module will respond when addressed by a
master. If the LSB (GC) is set the TWI module will respond to the general call address (00h);
otherwise it ignores the general call address.
Table 20-3.
CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the TWI. The
AA bit must be set to enable the own slave address or the general call address acknowledge-
ment. STA, STO and SI must be cleared.
When SSADR and SSCON have been initialised, the TWI module waits until it is addressed by
its own slave address followed by the data direction bit which must be at logic 0 (W) for the TWI
to operate in the slave receiver mode. After its own slave address and the W bit have been
received, the serial interrupt flag is set and a valid status code can be read from SSCS. This sta-
tus code is used to vector to an interrupt service routine.The appropriate action to be taken for
each of these status code is detailed in Table . The slave receiver mode may also be entered if
arbitration is lost while TWI is in the master mode (states 68h and 78h).
If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1) to SDA
after the next received data byte. While AA is reset, the TWI module does not respond to its own
slave address. However, the 2-wire bus is still monitored and address recognition may be
resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate
the module from the 2-wire bus.
bit rate
CR2
A6
SSADR: Slave Receiver Mode Initialization
SSCON: Slave Receiver Mode Initialization
SSIE
A5
1
STA
A4
0
own slave address
STO
A3
0
A2
SI
0
AA
A1
1
bit rate
CR1
A0
4337K–USB–04/08
bit rate
CR0
GC

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