AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 148

• Manufacturer Part Number: AT89C5130A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5130A-M

• Flash (kbytes): 16 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

148
AT89C5130A/31A-M
Table 21-14. UEPINT Register
Reset Value = 00h
Bit Number
7
7
6
5
4
3
2
1
0
-
Mnemonic
UEPINT (S:F8h read-only)
USB Endpoint Interrupt Register
EP6INT
EP6INT
EP5INT
EP4INT
EP3INT
EP2INT
EP1INT
EP0INT
Bit
6
-
Description
Reserved
The value read from this bit is always 0. Do not set this bit.
Endpoint 6 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 6. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP6IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 5 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 5. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP5IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 4 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 4. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP4IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 3 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 3. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP3IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 2 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 1 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
Endpoint 0 Interrupt
This bit is set by hardware when an endpoint interrupt source has been detected on the
endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be:
TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are cleared
EP5INT
5
EP4INT
4
EP3INT
3
EP2INT
2
EP1INT
1
4337K–USB–04/08
EP0INT
0