AT89C5131A-M Atmel Corporation, AT89C5131A-M Datasheet - Page 99

• Manufacturer Part Number: AT89C5131A-M
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-M

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

19.3.5
19.3.5.1
4337K–USB–04/08
Registers
Serial Peripheral Control Register (SPCON)
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent
with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt
requests.
Figure 19-7 gives a logical view of the above statements.
Figure 19-7. SPI Interrupt Requests Generation
There are three registers in the module that provide control, status and data storage functions. These registers are
describes in the following paragraphs.
Table 19-3 describes this register and explains the use of each bit.
Table 19-3.
• The Serial Peripheral Control Register does the following:
Number
SPR2
Bit
7
6
5
4
3
7
– Selects one of the Master clock rates
– Configure the SPI module as Master or Slave
– Selects serial clock polarity and phase
– Enables the SPI module
– Frees the SS pin for a general-purpose
Bit Mnemonic
SPCON Register
SSDIS
MSTR
SPEN
CPOL
SPEN
SPR2
SPIF
MODF
SSDIS
6
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit has no
effect if CPHA = “0”.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
Cleared to have the SCK set to “0” in idle state.
Set to have the SCK set to “1” in idle state.
SSDIS
5
SPI Transmitter
CPU Interrupt Request
SPI Receiver/Error
CPU Interrupt Request
MSTR
4
CPOL
3
AT89C5130A/31A-M
CPU Interrupt Request
CPHA
2
SPI
SPR1
1
SPR0
0
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