AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 144
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AT89C5132
Manufacturer Part Number
AT89C5132
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5132.pdf
(3 pages)
2.AT89C5132.pdf
(182 pages)
3.AT89C5132.pdf
(38 pages)
4.AT89C5132.pdf
(33 pages)
Specifications of AT89C5132
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-12C
Max I/o Pins
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Uart
1
Adc Channels
2
Adc Resolution (bits)
10
Adc Speed (ksps)
22.7
Sram (kbytes)
2.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 3.6
Timers
2
Isp
UART/USB
Watchdog
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Table 24. Status for Slave Transmitter Mode
Table 25. Status for Miscellaneous States
144
SSSTA
SSSTA
Status
Status
Code
Code
A8h
B0h
B8h
C0h
C8h
F8h
00h
Status of the TWI Bus
and TWI Hardware
Own SLA+R has been
received; ACK has
been returned
Arbitration lost in
SLA+R/W as master;
own SLA+R has been
received; ACK has
been returned
Data Byte in SSDAT
has been transmitted;
ACK has been
received
Data Byte in SSDAT
has been transmitted;
NOT ACK has been
received
Last data Byte in
SSDAT has been
transmitted
(SSAA= 0); ACK has
been received
Status of the TWI Bus
and TWI Hardware
No relevant state
information available;
SSI = 0
Bus error due to an
illegal START or STOP
condition
AT89C5132
To/From SSDAT
Write data Byte
Write data Byte
Write data Byte
Write data Byte
Write data Byte
Write data Byte
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
To/From SSDAT
No SSDAT action
No SSDAT action
Application Software Response
Application Software Response
SSSTA
SSSTA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
No SSCON action
SSSTO
SSSTO
To SSCON
To SSCON
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SSI
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
SSAA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Next Action Taken by TWI Hardware
Last data Byte will be transmitted.
Data Byte will be transmitted.
Last data Byte will be transmitted.
Data Byte will be transmitted.
Last data Byte will be transmitted.
Data Byte will be transmitted.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Next Action Taken by TWI Hardware
Wait or proceed current transfer.
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the bus is
released and SSSTO is reset.
4173E–USB–09/07