AT89C5132 Atmel Corporation, AT89C5132 Datasheet - Page 47
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AT89C5132
Manufacturer Part Number
AT89C5132
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5132.pdf
(3 pages)
2.AT89C5132.pdf
(182 pages)
3.AT89C5132.pdf
(38 pages)
4.AT89C5132.pdf
(33 pages)
Specifications of AT89C5132
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-12C
Max I/o Pins
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Uart
1
Adc Channels
2
Adc Resolution (bits)
10
Adc Speed (ksps)
22.7
Sram (kbytes)
2.25
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 3.6
Timers
2
Isp
UART/USB
Watchdog
Yes
Available stocks
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11.4.1
11.4.2
Figure 11-3. Power-down Exit Waveform Using INT1:0
Figure 11-4. Power-down Exit Waveform Using KIN3:0
Note:
4173E–USB–09/07
1. KIN3:0 can be high or low-level triggered.
Entering Power-down Mode
Exiting Power-down Mode
KIN3:0
INT1:0
OSC
OSC
1
To enter Power-down mode, set PD bit in PCON register. The AT89C5132 enters the Power-
down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is
the last instruction executed.
If V
restored to the normal operating level.
There are 2 ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
Note:
2. Generate a reset.
Active phase
Active phase
DD
–
was reduced during the Power-down mode, do not exit Power-down mode until V
1. The external interrupt used to exit Power-down mode must be configured as level sensitive
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM
The AT89C5132 provides capability to exit from Power-down using INT0, INT1, and
KIN3:0 inputs. In addition, using KIN input provides high or low level exit capability
(see Section “Keyboard Interface”, page 181).
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTn input, execution resumes when the
input is released (see Figure 11-3) while using KINx input, execution resumes after
counting 1024 clock ensuring the oscillator is restarted properly (see Figure 11-4).
This behavior is necessary for decoding the key while it is still pressed. In both
cases, execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Power-down mode.
(
interrupt must be long enough to allow the oscillator to stabilize. The execution will only
resume when the interrupt is deasserted.
content.
INT0
and
Power-down Phase
Power-down
INT1
) and must be assigned the highest priority. In addition, the duration of the
1024 clock count
Oscillator Restart
Active phase
Active Phase
AT89C5132
DD
47
is