AT89C51AC3 Atmel Corporation, AT89C51AC3 Datasheet
AT89C51AC3
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AT89C51AC3 Summary of contents
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... Packages: VQFP44, PLCC44, VQFP64, PLCC52 Description The AT89C51AC3 is a high performance Flash version of the 80C51 single chip 8-bit microcontrollers mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the AT89C51AC3 provides 64K Bytes of Flash memory including In-System Programming (ISP) and IAP, 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM ...
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... Block Diagram XTAL1 XTAL2 ALE PSEN AT89C51AC3 2 RAM Flash Boot UART 256x8 64k x 8 loader 2kx8 C51 CORE IB-bus CPU Timer 0 INT Parallel I/O Ports and Ext. Bus Timer 1 Ctrl Port 0Port 1 Port 2 Port 3 Notes analog Inputs/8 Digital I/O 2. 5-Bit I/O Port ...
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Pin Configuration 4383D–8051–02/08 P1.4/AN4/CEX1 7 P1.5/AN5/CEX2 8 P1.6/AN6/CEX3 9 P1.7/AN7/CEX4 P3.0/RxD 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.4/AN4/CEX1 1 P1.5/AN5/CEX2 2 P1.6/AN6/CEX3 3 P1.7/AN7/CEX4 4 ...
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... AT89C51AC3 P1.4/AN4/CEX1 8 P1.5/AN5/CEX2 9 P1.6/AN6/CEX3 10 P1.7/AN7/CEX4 PLCC52 P3.0/RxD 14 P4.3/SCK 15 P3.1/TxD 16 P3.2/INT0 17 P3.3/INT1 18 P3.4/T0 19 P3.5/T1/ TESTI must be connected to VSS P1.4/AN4/CEX1 P1.5/AN5/CEX2 3 P1.6/AN6/CEX3 4 P1.7/AN7/CEX4 VQFP64 P3.0/RxD 10 P4.3/SCK 11 P3.1/TxD 12 P3.2/INT0 13 P3.3/INT1 14 P3 ...
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Pin Name Type Description VSS GND Circuit ground TESTI I Must be connected to VSS VCC Supply Voltage VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 8-bit open drain bi-directional I/O port. ...
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... P4.0: Regular Port I/O P4.1: Regular Port I/O P4.2/MISO: Master Input Slave Output of SPI controller P4.3/SCK: Serial Clock of SPI controller P4.4/MOSI: Master Ouput Slave Input of SPI controller It can drive CMOS inputs without external pull-ups. AT89C51AC3 6 , see section "Electrical Characteristic") because of the internal pull-ups. IL 4383D–8051–02/08 ...
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... I When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level, AT89C51AC3 fetches all instructions from the external program memory XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. ...
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... Port 0 and Port 2 AT89C51AC3 8 Figure 1. Port 1, Port 3 and Port 4 Structure READ LATCH INTERNAL D P1.X Q BUS P3.X P4.X LATCH WRITE CL TO LATCH READ PIN Note: The internal pull-up can be disabled on P1 when analog function is selected. Ports 0 and 2 are used for general-purpose I the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups ...
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Read-Modify-Write Instructions 4383D–8051–02/08 Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL READ LATCH INTERNAL BUS D Q P2.X LATCH WRITE TO LATCH READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus ...
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... Quasi-Bidirectional Port Operation AT89C51AC3 10 write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’ ...
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... CDh byte Timer/Counter 2 Low TL2 CCh byte Timer/Counter 0 and TCON 88h 1 control Timer/Counter 0 and TMOD 89h 1 Modes 4383D–8051–02/08 The Special Function Registers (SFRs) of the AT89C51AC3 fall into the following categories – – – – – – – ...
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... PCA Compare Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L CCAP2L ECh PCA Compare Capture Module 2 L CCAP3L EDh PCA Compare Capture Module 3 L CCAP4L EEh PCA Compare Capture Module 4 L AT89C51AC3 TF2 EXF2 RCLK TCLK – – – – ...
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Mnemonic Add Name Interrupt Enable IEN0 A8h Control 0 Interrupt Enable IEN1 E8h Control 1 Interrupt Priority IPL0 B8h Control Low 0 Interrupt Priority IPH0 B7h Control High 0 Interrupt Priority IPL1 F8h Control Low 1 Interrupt Priority IPH1 F7h ...
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... Reserved Note not read or write Reserved Registers 2. These registers are bit addressable. – Sixteen addresses in the SFR space are both byte whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF. AT89C51AC3 14 2/A 3/B 4/C CCAP0H CCAP1H CCAP2H 0000 0000 ...
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... Clock Description 4383D–8051–02/08 The AT89C51AC3 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • ...
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... Figure 5. Clock CPU Generation Diagram Hardware byte CKCON.0 XTAL1 XTAL2 PD PCON.1 ÷ CKCON.0 SPIX2 CKCON1.0 AT89C51AC3 16 X2B PCON.0 On RESET IDL X2 0 ÷ ÷ 2 ÷ ÷ ÷ WDX2 PCAX2 SIX2 CKCON0.6 CKCON0.5 CKCON0.4 CKCON0.3 CPU Core ...
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Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a ...
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... Registers AT89C51AC3 18 Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register WDX2 PCAX2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bits is indeterminate. Do not set this bit. WatchDog clock 6 WDX2 Clear to select 6 clock periods per peripheral clock cycle. ...
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Table 3. CKCON1 Register CKCON1 (S:9Fh) Clock Control Register Bit Bit Number Mnemonic Description Reserved 7-1 - The value read from these bits is indeterminate. Do not set these bits. (1) SPI clock Clear to ...
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... Data Memory AT89C51AC3 20 The AT89C51AC3 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 2048 Bytes RAM segment (ERAM). ...
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Internal Space Lower 128 Bytes RAM Upper 128 Bytes RAM Expanded RAM 4383D–8051–02/08 The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are ...
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... WR# O Write signal output to external memory. This section describes the bus cycles the AT89C51AC3 executes to read (see Figure 11), and write data (see Figure 12) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor- mation on X2 mode ...
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Figure 11. External Data Read Waveforms CPU Clock ALE RD#1 P0 DPL Notes: 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. ...
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... Application AT89C51AC3 24 The AT89C51AC3 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 13) ...
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Registers 4383D–8051–02/08 Table 6. PSW Register PSW (S:8Eh) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 AC ...
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... AT89C51AC3 26 Bit Bit Number Mnemonic Description ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 4-2 XRS1-0 011 1024 Bytes 100 1792 Bytes 101 2048 Bytes (default configuration after reset) 110 Reserved 111 ...
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Power Monitor Description Figure 14. Power Monitor Block Diagram 4383D–8051–02/08 The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power sup- ply falls below a ...
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... Figure 15. Power Fail Detect Vcc Reset Vcc AT89C51AC3 28 When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 lev- els are above and below VIH and VIL ...
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... Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51AC3 datasheet. The status of the Port pins during reset is detailed in Table 9. Figure 17. Reset Circuitry and Power-On Reset RST VSS a ...
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... RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit kΩ resis- tor must be added as shown Figure 18. Figure 18. Recommended Reset Output Schematic VDD + RST VDD 1K RST VSS AT89C51AC3 To other on-board circuitry 4383D–8051–02/08 ...
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... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 9. To enter Idle mode, set the IDL bit in PCON register (see Table 10). The AT89C51AC3 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
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... OSC Active phase AT89C51AC3 32 To enter Power-Down mode, set PD bit in PCON register. The AT89C51AC3 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level ...
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Table 9. Pin Conditions in Special Operating Modes Mode Port 0 Port 1 Reset Floating High Idle (internal Data Data code) Idle (external Floating Data code) Power- Down(inter Data Data nal code) Power- Down Floating Data (external code) Port ...
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... Registers AT89C51AC3 34 Table 10. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-4 - The value read from these bits is indeterminate. Do not set these bits. General Purpose flag 1 3 GF1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode ...
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EEPROM Data Memory Write Data in the Column Latches Programming Read Data 4383D–8051–02/08 The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the ...
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... Examples AT89C51AC3 36 ;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM space MOVX A, @DPTR MOV EECON, #00h; unmap EEPROM ret ;*F************************************************************************* ...
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Registers 4383D–8051–02/08 Table 11. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. Reserved ...
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... Program/Code Memory AT89C51AC3 38 The AT89C51AC3 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD volt- age ...
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... This signal is active low during external code fetch or external code read (MOVC instruction). This section describes the bus cycles the AT89C51AC3 executes to fetch code (see Figure 22) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor- mation on X2 mode see section “ ...
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... Extra Row (128 Bytes) Column Latches (128 Bytes) AT89C51AC3 40 PCL D7:0 PCH AT89C51AC3 features two on-chip Flash memories: • Flash memory FM0: containing 64K Bytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API). ...
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Figure 24. Flash Memory Architecture with ENBOOT=0 (user modemode) Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 4383D–8051–02/08 FFFFh 64K Bytes F800h FM0 0000h Memory space not accessible FFFFh 2K Bytes Flash memory boot space FM1 ...
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... FM0 Memory Architecture User Space Extra Row (XRow) Hardware security Byte (HSB) Column Latches Cross Flash Memory Access Description AT89C51AC3 42 The Flash memory is made blocks (see Figure 23): • The memory array (user space) 64K Bytes • The Extra Row • ...
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Cross Flash Memory Access Action Read Load column latch FM0 (user Flash) Write Read Load column latch FM1 (boot Flash) Write Read External Load column latch memory Write (a) Depend upon general lock bit configuration. FM0 ...
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... Overview of FM0 Operations Flash Registers (SFR) FCON Register AT89C51AC3 44 The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA in the working data or code space. ...
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... Notes: 1. The column latches reset is a new option introduced in the AT89C51AC3, and is not available in T89C51CC01/2 FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5xh followed by Axh. Table 16 summarizes the memory spaces to program according to FMOD1:0 bits ...
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... Status of the Flash Memory Selecting FM1 Loading the Column Latches AT89C51AC3 46 Table 16. Programming Spaces Write to FCON FPL3:0 FPS User Extra Row Hardware 5 X Security A X Byte Reset 5 X Columns A X Latches Notes: 1. The sequence 5xh and Axh must be executing without instructions between them otherwise the programming is not executed (see Flash Status Register) 2 ...
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The page address of the last address loaded in the column latches will be used for the whole page. When programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, ...
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... Programming the Flash Spaces User Extra Row AT89C51AC3 48 Figure 25. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is used to program the User space and is summarized in Figure 26: • ...
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Hardware Security Byte 4383D–8051–02/08 Figure 26. Flash and Extra Row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 27: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and ...
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... Reset the Column Latches Error Reports Flash Programming Sequence Errors AT89C51AC3 50 Figure 27. Hardware Programming Procedure Flash Spaces Programming Save and Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A End Loading Restore IT An automatic reset of the column latches is performed after a successful Flash write sequence ...
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Power Down Request Reading the Flash Spaces User Extra Row Hardware Security Byte Flash Protection from Parallel Programming 4383D–8051–02/08 Before entering in Power Down (Set bit PD in PCON register) the user should check that no write sequence is in ...
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... AT89C51AC3 52 Table 17. Program Lock Bit Program Lock Bits Security LB0 LB1 LB2 level Protection Description program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory sampled and latched on reset, and further parallel programming of the Flash is disabled ...
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Operation Cross Memory Access Table 18. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write External Read memory Write or Code Roll Over Note: 1. RWW: Read While Write 4383D–8051–02/08 Space addressable in read ...
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... Sharing Instructions AT89C51AC3 54 Table 19. Instructions shared XRAM EEPROM Action RAM ERAM DATA Read MOV MOVX MOVX Write MOV MOVX MOVX Note using Column Latch Table 20. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register ENBOOT Table 21. Write MOVX @DPTR,A ...
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Table 22. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 FMOD0 From FM0 From FM1 (ENBOOT = External code : X 0 EA=0 ...
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... With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C51AC3 allows the system engineer the development of applica- tions with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • ...
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Hardware Boot Process 4383D–8051–02/08 Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - ...
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... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are describe in an documentation: "In-System Programing: Flash Library for AT89C51AC3" available on the Atmel web site. Table 23. XROW Mapping Description Copy of the Manufacturer Code ...
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Hardware Security Byte 4383D–8051–02/08 Table 24. Hardware Security Byte X2B BLJB - Bit Bit Number Mnemonic Description X2 Bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 mode. ...
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... Figure 32. Framing Error Block Diagram AT89C51AC3 60 The AT89C51AC3 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
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Automatic Address Recognition 4383D–8051–02/08 Figure 33. UART Timing in Mode 1 RXD D0 D1 Start bit RI SMOD0=X FE SMOD0=1 Figure 34. UART Timing in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 ...
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... Given Address Broadcast Address AT89C51AC3 62 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time ...
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Registers 4383D–8051–02/08 For slaves A and B, bit don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A ...
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... AT89C51AC3 64 Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register – – – Bit Bit Number Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 27. SADDR Register SADDR (S:A9h) Slave Address Register – ...
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Table 29. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 – Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...
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... Timer 0 AT89C51AC3 66 The AT89C51AC3 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. ...
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Mode 0 (13-bit Timer) Figure 35. Timer/Counter Mode 0 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 36. Timer/Counter x ...
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... FTx ÷ 6 CLOCK See the “Clock” section AT89C51AC3 68 Mode 2 configures Timer 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0 ...
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Timer 1 Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) 4383D–8051–02/08 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol- lowing ...
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... Interrupt Registers AT89C51AC3 70 Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting interrupts are globally enabled by setting EA bit in IEN0 register. ...
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Table 31. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set ...
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... AT89C51AC3 72 Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 33. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register – – – Bit Bit ...
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Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b – – ...
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... T2 AT89C51AC3 74 The AT89C51AC3 timer 2 is compatible with timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected controlled by T2CON register (See Table ) and T2MOD register (See Table 38). Timer 2 operation is similar to Timer 0 and Timer 1 ...
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Programmable Clock- Output Figure 41. Clock-Out Mode FT2 CLOCK T2 T2EX 4383D–8051–02/08 In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (See Figure 41). The input clock increments TL2 at frequency F repeatedly counts to overflow ...
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... Registers AT89C51AC3 76 Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
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Table 37. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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... AT89C51AC3 78 Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 40. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register Bit Bit Number Mnemonic Description 7-0 High Byte of Timer 2 Reload/Capture ...
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... Fwd Clock - 4383D–8051–02/08 AT89C51AC3 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. ...
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... Watchdog Programming AT89C51AC3 80 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42. Machine Cycle Count compute WD Time-Out, the following formula is applied: ---------------------------------------------------------------- - FTime Out – × ( Note: ...
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... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting AT89C51AC3 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...
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... AT89C51AC3 82 Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register – – – Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences. ...
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Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) 4383D–8051–02/08 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and ...
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... Baud Rate AT89C51AC3 Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. ...
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Functional Description Figure 44. SPI Module Block Diagram SPSCR SPIF - OVR SPI Control SPCON SPR2 SPEN SSDIS Operating Modes 4383D–8051–02/08 Figure 44 shows a detailed structure of the SPI Module. Internal Bus UARTM SPTEIE MODFIE MODF SPTE MSTR CPOL ...
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... Master Mode Slave Mode Transmission Formats AT89C51AC3 86 When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 45) ...
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Figure 46. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 47. Data Transmission Format (CPHA = 1) ...
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... MISO Data Byte 1 BYTE 1 under transmission SPTE AT89C51AC3 88 When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared ...
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Error Conditions Mode Fault Error (MODF) 4383D–8051–02/08 The following flags in the SPSCR register indicate the SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the ...
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... OverRun Condition Interrupts AT89C51AC3 90 Figure 51. Mode Fault Conditions in Slave Mode 0 SCK cycle # 1 SCK z 0 (from master) 1 MOSI z (from master MISO MSB z (from slave (slave) 0 MODF detected Note: when SS is discarded (SS disabled not possible to detect a MODF error in slave mode because the SPI is internally selected ...
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Registers Serial Peripheral Control Register (SPCON) 4383D–8051–02/08 Figure 52. SPI Interrupt Requests Generation SPIF SPTEIE SPTE MODFIE MODF Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs. • ...
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... Serial Peripheral Status Register and Control (SPSCR) AT89C51AC3 92 Bit Number Bit Mnemonic Description Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. Clock Phase Cleared to have the data sampled when the SCK leaves the idle ...
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Bit Bit Number Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading SPSCR 4 MODF When MODF ...
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... Programmable Counter Array (PCA) PCA Timer AT89C51AC3 94 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules ...
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Figure 53. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle PCA Modules 4383D–8051–02/08 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which ...
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... Module 1 Module 2 Module 3 Module 4 CMOD.0 PCA Capture Mode AT89C51AC3 96 Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. • The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. • ...
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Figure 55. PCA Capture Mode CEXn 16-bit Software Timer Mode Figure 56. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to ...
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... Enable Pulse Width Modulator Mode AT89C51AC3 98 In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set ...
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Figure 58. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) PCA WatchDog Timer 4383D–8051–02/08 CCAPnH CCAPnL 8-Bit Comparator ECOMn CCAPMn.6 CCAPMn.1 An on-board WatchDog timer is available with the PCA ...
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... PCA Registers AT89C51AC3 100 Table 50. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL WDTE - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. ...
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Table 51. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA 7 ...
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... AT89C51AC3 102 Table 52. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 Bit Bit Number Mnemonic Description CCAPnH 7:0 High byte of EWC-PCA comparison or capture values 7:0 Reset Value = 0000 0000b Table 53 ...
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Table 54. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read from ...
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... AT89C51AC3 104 Table 55. CH Register CH (S:F9h) PCA Counter Register High Value Bit Bit Number Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 56. CL Register CL (S:E9h) PCA counter Register Low Value Bit ...
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... This section describes the on-chip 10 bit analog-to-digital converter of the AT89C51AC3. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC ...
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... ADCON.0 Figure 60 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the AT89C51AC3 datasheet. T CONV ADC ADCON ...
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ADC Converter Operation Voltage Conversion Clock Selection 4383D–8051–02/08 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is ...
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... CPU CLOCK CPU Core Clock Symbol ADC Standby Mode IT ADC Management Routines examples AT89C51AC3 108 Prescaler ADCLK ÷ 2 When the ADC is not used possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1 µW. ...
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EADC = 1 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt ...
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... Registers AT89C51AC3 110 Table 58. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 7-0 CH 0:7 Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. Reset Value =0000 0000b Table 59. ADCON Register ADCON (S:F3h) ADC Control Register ...
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Table 60. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler 4-0 ...
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... AT89C51AC3 112 Bit Bit Number Mnemonic Description Reserved 7-2 - The value read from these bits are indeterminate. Do not set these bits. ADC result 1-0 ADAT1:0 bits 1-0 Reset Value = 00h 4383D–8051–02/08 ...
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Interrupt System Introduction Figure 63. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:5 PCA TxD UART RxD Timer AIN1:0 Converter SPI Controller 4383D–8051–02/08 The Micro-controller has a total ...
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... AT89C51AC3 114 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers ...
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Registers 4383D–8051–02/08 Table 65. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, ...
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... AT89C51AC3 116 Table 66. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
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Table 67. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority ...
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... AT89C51AC3 118 Table 68. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...
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Table 69. IPL0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...
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... AT89C51AC3 120 Table 70. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...
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Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias industrial ....................................................... -40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage on V from V ......................................-0. Voltage on Any Pin from V ...
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... OL Port Ports and Maximum total I for all output pins exceeds the test condition than the listed test conditions. AT89C51AC3 122 Min I = 0.4 Frequency (MHz CCOP I = 0.2 Frequency (MHz CCIDLE . I would be slightly higher if a crystal oscillator used (see Figure ...
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DC Parameters for A/D Converter 4383D–8051–02/08 Figure 65. I Test Condition, Idle Mode CC V RST (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 66. I Test Condition, Power-Down Mode RST EA XTAL2 ...
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... AC Parameters Explanation of the AC Symbols AT89C51AC3 124 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for ...
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External Program Memory Characteristics 4383D–8051–02/08 Table 73. Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ...
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... External Program Memory Read Cycle T ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 AT89C51AC3 126 Table 75. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min PLPH T Max PLIV T Min PXIX T Max PXIZ ...
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External Data Memory Characteristics 4383D–8051–02/08 Table 76. Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ ...
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... AT89C51AC3 128 Table 78. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T Max LLDV T Max AVDV T Min LLWL T Max LLWL T Min AVWL T Min QVWX T Min QVWH T Min WHQX T Max RLAZ T Min WHLH T Max ...
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External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing – Shift Register Mode 4383D–8051–02/08 T LLWL ...
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... Shift Register Timing Waveforms INSTRUCTION ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) AT89C51AC3 130 Table 80. AC Parameters for a Fix Clock ( MHz) Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 81. AC Parameters for a Variable Clock ...
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External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms 4383D–8051–02/08 V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made at ...
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... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51AC3 132 Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. STATE5 ...
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Flash/EEPROM Memory 4383D–8051–02/08 Table 83. Timing Symbol Definitions Signals S (Hardware PSEN#,EA condition) R RST B FBUSY flag Table 84. Memory AC Timing VDD = 3V to 5.5V -40 to +85°C Symbol Parameter T Input PSEN# Valid to ...
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... UART AT89C51AC3-RDTUM UART AT89C51AC3-S3SUM UART AT89C51AC3 134 Temperature Range Package OBSOLETE Industrial & Green VQFP44 Industrial & Green PLCC44 Industrial & Green VQFP64 Industrial & Green PLCC52 Packing Product Marking Tray AT89C51AC3-M Stick AT89C51AC3-IM Tray AT89C51AC3-IM Stick AT89C51AC3-IM 4383D–8051–02/08 ...
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Package Drawing VQFP44 4383D–8051–02/08 135 ...
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... PLCC44 AT89C51AC3 136 4383D–8051–02/08 ...
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VQFP64 4383D–8051–02/08 137 ...
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... PLCC52 AT89C51AC3 138 4383D–8051–02/08 ...
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Document Revision History Changes from 4383A 10/04 - 4383B 01/05 Changes from 4383B 01/05 to 4383C 11/05 Changes from 4383C 11/05 to 4383D 02/08 4383D–8051–02/08 1. Various minor corrections made throughout the document. 2. Clarification to Mode Switching Waveforms diagram. ...
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... Atmel Corporation 2008. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...