AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 131
AT89LP51RC2
Manufacturer Part Number
AT89LP51RC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51RC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
1.375
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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18.4.4
18.5
Figure 18-3. SPI Transfer Format with CPHA = 0
Note:
Figure 18-4. SPI Transfer Format with CPHA = 1
Note:
3722A–MICRO–10/11
Serial Clock Timing
*Not defined but normally MSB of character just received.
(FOR REFERENCE)
*Not defined but normally LSB of previously transmitted character.
SS Error Flag (SSERR)
(FROM MASTER)
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
(FROM SLAVE)
SCK CYCLE #
MOSI
MISO
A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data
in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit
(reset of the SPI state machine).
The CPHA, CPOL and SPR bits in SPCON control the shape and rate of SCK. The two SPR bits
provide four possible clock rates when the SPI is in master mode. In slave mode, the SPI will
operate at the rate of the incoming SCK as long as it does not exceed the maximum bit rate.
There are also four possible combinations of SCK phase and polarity with respect to the serial
data. CPHA and CPOL determine which format is used for transmission. The SPI data transfer
formats are shown in
interface, CPHA, CPOL, and SPR should not be modified while the interface is enabled, and the
master device should be enabled before the slave device(s).
*
MSB
MSB
1
Figures 18-3 and
2
6
6
AT89LP51RB2/RC2/IC2 Preliminary
3
5
5
4
4
4
18-4. To prevent glitches on SCK from disrupting the
5
3
3
6
2
2
7
1
1
8
LSB
LSB
131
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