AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 176
AT89LP51RC2
Manufacturer Part Number
AT89LP51RC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51RC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
1.375
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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AT89LP51RB2/RC2/IC2 Preliminary
Table 22-1.
Notes:
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
Branching
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
JZ rel
JNZ rel
SJMP rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
JMP @A+DPTR
JMP @A+PC
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
CJNE A, @R0, rel
CJNE A, @R1, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
1. A clock cycle is one period of the output of the system clock divider. For Fast mode the divider
defaults to 1, so the clock cycle equals the oscillator period. For Compatibility mode the divider
(2)
Instruction Execution Times and Exceptions
(2)
(2)
Bytes
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
2
2
2
2
3
1
1
2
3
1
2
3
3
3
3
3
3
2
3
1
Compatibility
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
18
18
12
12
6
6
6
6
6
6
(1)
Clock Cycles
(Continued)
Fast
1
2
1
2
2
2
2
2
2
2
3
3
4
4
3
3
3
3
4
4
4
3
4
2
3
4
4
4
4
4
3
4
1
4
4
3722A–MICRO–10/11
11,31,51,71,91,
01,21,41,61,81,
Hex Code
A1,C1,E1
B1,D1,F1
D8-DF
B8-BF
B6-B7
A5 B6
A5 B7
A5 73
D3
D2
B3
B2
B0
A0
A2
B5
B4
D5
82
72
92
40
50
20
30
10
60
70
80
12
22
32
02
73
00
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