AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 180
AT89LP51RC2
Manufacturer Part Number
AT89LP51RC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51RC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
1.375
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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22.1.7
22.1.8
180
Description: The forty bits in the M register are shifted one bit to the left. Bit 0 is cleared. No flags are affected.
Description: The MOVC instructions load the Accumulator with a code byte or constant from program memory. The address
Operation: LSL
Operation: MOVC
Encoding:
Encoding:
AT89LP51RB2/RC2/IC2 Preliminary
Function: Shift MAC Accumulator Left Logically
Function: Move code byte relative to Alternate Data Pointer
LSL M
MOVC A, @A+/DPTR
Example: The M register holds the value 0C5B1A29384H. The following instruction,
Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the
Cycles: 2
Cycles: 4
Bytes: 2
Bytes: 2
LSL M
leaves the M register holding the value 8B63452708H.
(M
(M
of the byte fetched is the sum of the original unsigned 8-bit Accumulator contents and the contents of the
unselected Data Pointer. The base register is not altered. Sixteen-bit addition is performed so a carry-out from
the low-order eight bits may propagate through higher-order bits. No flags are affected.
Accumulator to one of four values defined by the DB (define byte) directive.
TABLE:
If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator.
IF (DPS) = 0
THEN
ELSE
n+1
0
) ← 0
A5
A5
MOV
MOVC
RET
(A) ← ( (A) + (DPTR1) )
(A) ← ( (A) + (DPTR0) )
) ← (M
DB
DB
DB
DB
n
) n = 0 - 38
66H
/DPTR, #TABLE
A, @A+PC
77H
88H
99H
0
1
0
0
1
0
0
1
0
0
0
0
1
1
1
1
3722A–MICRO–10/11
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