AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 22
AT89LP51RC2
Manufacturer Part Number
AT89LP51RC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51RC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
1.375
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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3.4
Table 3-3.
22
Symbol
PAGE
PAGE = F6H
Not Bit Addressable
Bit
7-0
Extra RAM (EDATA)
AT89LP51RB2/RC2/IC2 Preliminary
Function
Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions when PAGE < 08H. Any PAGE
value between 08H and FFH will selected XDATA; however, this value will not be output on P2.
PAGE
—
7
– EDATA Page Register
Figure 3-15. MOVX with Three Wait States (WS = 11B)
The Extra RAM is a portion of the external memory space implemented as an internal 2K byte
auxiliary RAM. The Extra RAM is mapped into the EDATA space at the bottom of the external
memory address space, from 0000H to 07FFH, when EXTRAM = 0 (AUXR.1). The size of
EDATA can be reduced by the XRS bits in AUXR (See
address range will access the internal Extra RAM. EDATA can be accessed with both 16-bit
(MOVX @DPTR) and 8-bit (MOVX @Ri) addresses. When 8-bit addresses are used, the PAGE
register (0F6H) supplies the upper address bits. The PAGE register breaks EDATA into eight
256-byte pages. A page cannot be specified independently for MOVX @R0 and MOVX @R1.
Setting PAGE above 07H enables XDATA access, but does not change the value of Port 2.
When 16-bit addresses are used (DPTR), the EEE bit (EECON.1) must also be zero to access
EDATA. MOVX instructions to EDATA require a minimum of 2 clock cycles.
CLK
ALE
WR
RD
P2
P0
P0
—
6
P2 SFR
P0 SFR
P0 SFR
S1
—
DPL OUT
DPL OUT
5
S2
S3
—
4
W1
DPH or P2 OUT
PAGE.3
DATA OUT
FLOAT
W2
3
W3
PAGE.2
2
Table
S4
3-2). MOVX instructions to this
Reset Value = 0000 0000B
P2 SFR
P0 SFR
P0 SFR
PAGE.1
1
PAGE.0
3722A–MICRO–10/11
0
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