AT89LP51RC2 Atmel Corporation, AT89LP51RC2 Datasheet - Page 82
AT89LP51RC2
Manufacturer Part Number
AT89LP51RC2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51RC2
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
1.375
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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13.4
13.5
82
Mode 2 – 8-bit Auto-Reload Timer/Counter
Mode 3 – 8-bit Split Timer
AT89LP51RB2/RC2/IC2 Preliminary
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown
in
TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the
same for Timer/Counter 0.
The following equation gives the timeout period for Mode 2. In Fast Mode, TPS applies only
when the TnX2 bits in CKCON0 are set. TPS always applies in Compatibility Mode, therefore
setting TnX2 in Compatibility Mode will double the timeout period.
Figure 13-3. Timer/Counter 1 Mode 2: 8-bit Auto-Reload
Note:
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in
Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is
shown in
is locked into a timer function (counting clock cycles) and takes over the use of TR1 and TF1
from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer 0 is in Mode 3, Timer 1
will still obey its settings in TMOD but cannot generate an interrupt.
Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the
AT89LP51RB2/RC2/IC2 can appear to have four Timer/Counters. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case,
Timer 1 can still be used by the serial port as a baud rate generator or in any application not
requiring an interrupt.
The following equation gives the timeout period for Mode 3. In Fast Mode, TPS applies only
when the TnX2 bits in CKCON0 are set. TPS always applies in Compatibility Mode, therefore
setting TnX2 in Compatibility Mode will double the timeout period.
Figure
CLK
INT0 Pin
RH1/RL1 are not required by Timer 1 during Mode 2 and may be used as temporary storage
registers.
Figure
13-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of
GATE1
T1 Pin
SYS
13-4. TL0 uses the Timer 0 control bits: C/T, GATE0, TR0, INT0, and TF0. TH0
Mode 2:
÷TPS
TR1
Mode 3:
C/T = 0
C/T = 1
Time-out Period
Time-out Period
Control
=
(
------------------------------- -
256 THn
=
(8 Bits)
(8 Bits)
TH1
TL1
f
---------- -
f
256
SYS
SYS
–
×
(
)
TPS
×
Reload
(
TPS
+
1
)
+
TF1
1
)
3722A–MICRO–10/11
Inter r up t
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