ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 10

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

4. General Circuit Description
Figure 4-1.
8111C–MCU Wireless–09/09
DIG3/4
RFP
RFN
DIG1/2
Analog Domain
AT86RF231 Block Diagram
LNA
AD
PA
This single-chip radio transceiver provides a complete radio transceiver interface between an
antenna and a microcontroller. It comprises the analog radio, digital modulation and demodula-
tion including time and frequency synchronization and data buffering. The number of external
components is minimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and
reception, thus no external antenna switch is needed.
The AT86RF231 block diagram is shown in
The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier
(LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter
(BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital
converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the
digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-
length block coding (spreading) according to
the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to
ensure the coherent phase modulation required for demodulation of O-QPSK signals. The fre-
quency-modulated signal is fed to the power amplifier (PA).
A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.
Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V
supply.
PPF
ext. PA and Power
Control
Antenna Diversity
PLL
BPF
XOSC
Limiter
AGC
FTN, BATMON
AVREG
TX Data
ADC
RSSI
Figure 4-1 on page
[1]
and [2]. The modulation signal is generated in
Digital Domain
RX BBP
TX BBP
Frame
Buffer
Configuration Registers
Control Logic
DVREG
10.
AES
(Slave)
AT86RF231
SPI
/SEL
MISO
MOSI
SCLK
IRQ
CLKM
DIG2
/RST
SLP_TR
10