ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 105

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

Figure 9-3.
9.2.5
8111C–MCU Wireless–09/09
Bit
+0x05
Read/Write
Reset Value
TRX_STATE
SLP_TR
PA buffer
PA
Modulation
Register Description
PLL_ON
TX Power Ramping
R/W
7
1
PA_BUF_LT
0
When using an external RF front-end (refer to
may be required to adjust the startup time of the external PA relative to the internal building
blocks to optimize the overall PSD. This can be achieved using register bits PA_BUF_LT and
PA_LT.
Register 0x05 (PHY_TX_PWR):
This register controls the output power and the ramping of the transmitter.
• Bit [7:6] - PA_BUF_LT
These register bits control the enable lead time of the internal PA buffer relative to the enable
time of the internal PA. This time is further used to derive a control signal for an external RF
front-end to switch between receive and transmit, for details refer to
Table 9-2.
R/W
Register Bits
PA_BUF_LT
6
1
2
R/W
5
0
4
PA Buffer Enable Time Relative to the PA
PA_LT
6
R/W
4
0
Value
0
1
2
3
8
R/W
3
0
BUSY_TX
10
PA_BUF_LT
Section 11.5 “RX/TX Indicator” on page
R/W
2
0
12
TX_PWR
PA Buffer Lead Time [µs]
14
R/W
PA_LT
1
0
0
2
4
6
Section
16
1 1
AT86RF231
0
R/W
11.5.
0
0
1 1
18
0 0
Length [µs]
PHY_TX_PWR
1 1
147) it
105