ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 109

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

9.3.3
8111C–MCU Wireless–09/09
Interrupt Handling
Access conflicts may occur when reading and writing data simultaneously at the two indepen-
dent ports of the Frame Buffer, TX/RX BBP and SPI. Both of these ports have their own address
counter that points to the Frame Buffer's current address.
Access violations occurs during concurrent Frame Buffer read or write accesses, when the SPI
port's address counter value becomes higher than or equal to that of TX/RX BBP port.
While receiving a frame, primarily the data needs to be stored in the Frame Buffer before read-
ing it. This can be ensured by accessing the Frame Buffer 32 µs after IRQ_2 (RX_START) at the
earliest. When reading the frame data continuously the SPI data rate shall be lower than 250
kb/s to ensure no under run interrupt occurs. To avoid access conflicts and to simplify the Frame
Buffer read access Frame Buffer Empty indication may be used, for details refer to
“Frame Buffer Empty Indicator” on page
While transmitting an access violation occurs during a Frame Buffer write access, when the SPI
port's address counter value becomes less than or equal to that of TX BBP port.
Both these access violations may cause data corruption and are indicated by IRQ_6 (TRX_UR)
interrupt when using the Frame Buffer access mode. Access violations are not indicated when
using the SRAM access mode.
Notes
• Interrupt IRQ_6 (TRX_UR) is valid 64 µs after IRQ_2 (RX_START). The occurrence of the
• If a Frame Buffer read access is not finished until a new frame is received, a TRX_UR
• When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be
interrupt can be disregarded when reading the first byte of the Frame Buffer between 32 µs
and 64 µs after the RX_START interrupt.
interrupt occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher
than the effective PHY data rate. A minimum SPI clock rate of 1 MHz is recommended in this
case. Finally, the microcontroller should check the integrity of the transferred frame data by
calculating the FCS.
higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU
data must be available in the Frame Buffer before SFD transmission is complete, which takes
176 µs (16 µs PA ramp up + 160 µs SHR) from the rising edge of SLP_TR pin (see
2 on page
39).
152.
AT86RF231
Section 11.7
Figure 7-
109