ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 129

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

11.1.3
11.1.4
11.1.4.1
8111C–MCU Wireless–09/09
Security Key Setup
Security Operation Modes
Electronic Code Book (ECB)
The encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM address
0x83, AES_CTRL or the mirrored version with SRAM address 0x94, AES_CTRL_MIRROR).
The AES module control registers are only accessible using SRAM read and write accesses on
address space 0x82 to 0x94. A configuration of the AES mode, providing the data and the start
of the operation can be combined within one SRAM access.
Notes
The setup of the key is prepared by setting register bits AES_MODE = 0x1 (SRAM address
0x83, AES_CTRL). Afterwards the 128 bit key must be written to SRAM addresses 0x84 through
0x93 (registers AES_KEY). It is recommended to combine the setting of control register 0x83
(AES_CTRL) and the 128 bit key transfer using only one SRAM access starting from address
0x83.
The address space for the 128-bit key and 128-bit data is identical from programming point of
view. However, both use different pages which are selected by register bit AES_MODE before
storing the data.
A read access to registers AES_KEY (0x84 - 0x93) returns the last round key of the preceding
security operation. After an ECB encryption operation, this is the key that is required for the cor-
responding ECB decryption operation. However, the initial AES key, written to the security
module in advance of an AES run, see step 1 in
an AES operation. This initial key is used for the next AES run even it cannot be read from
AES_KEY.
Note
ECB is the basic operating mode of the security module. After setting up the initial AES key, reg-
ister bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) sets up ECB mode. Register bit
AES_DIR (SRAM address 0x83, AES_CTRL) selects the direction, either encryption or decryp-
tion. The data to be processed has to be written to SRAM addresses 0x84 through 0x93
(registers AES_STATE).
An example for a programming sequence is shown in
assumes a suitable key has been loaded before.
• No additional register access is required to operate the security block.
• Using AES in TRX_OFF state requires an activated clock at pin 17 (CLKM), i.e. register bits
• Access to the security block is not possible while the radio transceiver is in state SLEEP.
• All configurations of the security module, the SRAM content and keys are reset during
• ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The
CLKM_CTRL!= 0. For further details refer to
(CLKM)” on page
SLEEP or RESET states.
AT86RF231 provides this functionality as an additional feature.
117.
Section 9.6.4 “Master Clock Signal Output
Table 11-1 on page
Figure 11-1 on page
128, is not modified during
AT86RF231
130. This example
129