ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 132

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

11.1.5
Figure 11-5. Packet Structure - Fast SRAM Access Mode
8111C–MCU Wireless–09/09
MOSI
MISO
Address
MOSI
MISO
Address
cmd add cfg
stat xx
PHY_STATUS
Data Transfer - Fast SRAM Access
byte 0 (cmd)
SRAM write
0x83
xx
AES access #0
P0
xx
address 0x83
byte 1 (addr.)
P1
xx
Note that IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only, as it
implements a one-way hash function.
The ECB and CBC modules including the AES core are clocked with 16 MHz. One AES opera-
tion takes 24 µs to execute, refer to parameter 12.4.15 in
Characteristics” on page
the transfer of the data via the SPI interface.
To reduce the overall processing time the AT86RF231 provides a Fast SRAM access for the
address space 0x82 to 0x94.
Note:
In contrast to a standard SRAM access, refer to
22, the Fast SRAM access allows writing and reading of data simultaneously during one SPI
access for consecutive AES operations (AES run).
For each byte P0 transferred to pin 22 (MOSI) for example in "AES access #1", see
on page 132
at pin 20 (MISO) with an offset of one byte.
In the example shown in
SRAM within "AES access #0". The last command on address 0x94 (AES_CTRL_MIRROR)
starts the AES operation ("AES run #0"). In the next "AES access #1" new plaintext data P0 -
P15 is written to the SRAM for the second AES run, in parallel the ciphertext C0 - C15 from the
first AES run is clocked out at pin MISO. To read the ciphertext from the last "AES run #(n)" one
dummy "AES access #(n+1)" is needed.
Note that the SRAM write access always overwrites the previous processing result.
The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to
0x94.
XX
...
...
...
P14
xx
Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94, see register
description AES_CTRL_MIRROR for details.
P15
xx
<AES_CTRL>
0x94
(lower part), the previous content of the respective AES register C0 is clocked out
byte 2 (cfg)
start
AES run #0
xx
0x83
XX
cmd add cfg
stat xx
157. That means that the processing of the data is usually faster than
Figure 11-5 on page 132
0x83
xx
P0[7:0]
byte 3
0x84
XX
AES access #1
P0
xx
P1
C0
...
...
...
P14
C13
P1[7:0]
C0[7:0]
byte 4
0x85
C14
P15
Section 6.2.3 “SRAM Access Mode” on page
0x94
start
C15
the initial plaintext P0 - P15 is written to the
AES run #n
...
...
Section 12.4 “Digital Interface Timing
cmd add cfg
stat xx
P15[7:0]
C14[7:0]
byte 18
0x93
0x83
xx
AES access #n+1
xx
xx
<AES_CTRL>
AT86RF231
byte 19 (start)
C0
xx
C15[7:0]
0x94
...
...
...
C13
xx
Figure 11-5
(1)
C14
xx
0x94
start
C15
132