ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 169

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

14. Register Summary
8111C–MCU Wireless–09/09
0x2C
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
SHORT_ADDR_0
SHORT_ADDR_1
PHY_ED_LEVEL
VERSION_NUM
PHY_TX_PWR
IEEE_ADDR_0
IEEE_ADDR_1
IEEE_ADDR_2
IEEE_ADDR_3
IEEE_ADDR_4
IEEE_ADDR_5
IEEE_ADDR_6
IEEE_ADDR_7
TRX_STATUS
PHY_CC_CCA
TRX_CTRL_0
TRX_CTRL_1
TRX_CTRL_2
IRQ_STATUS
XAH_CTRL_1
XAH_CTRL_0
CCA_THRES
SFD_VALUE
VREG_CTRL
XOSC_CTRL
TRX_STATE
PART_NUM
PHY_RSSI
IRQ_MASK
FTN_CTRL
RX_CTRL
MAN_ID_0
MAN_ID_1
PAN_ID_0
PAN_ID_1
BATMON
PLL_DCU
ANT_DIV
RX_SYN
PLL_CF
Name
-
-
-
-
-
MAX_FRAME_RETRES[3]
SHORT_ADDR_0[7]
SHORT_ADDR_1[7]
VERSION_NUM[7]
TRAC_STATUS[2]
RX_SAFE_MODE
MASK_BAT_LOW
PLL_DCU_START
IEEE_ADDR_0[7]
IEEE_ADDR_1[7]
IEEE_ADDR_2[7]
IEEE_ADDR_3[7]
IEEE_ADDR_4[7]
IEEE_ADDR_5[7]
IEEE_ADDR_6[7]
IEEE_ADDR_7[7]
RX_CRC_VALID
CCA_REQUEST
PLL_CF_START
XTAL_MODE[3]
SFD_VALUE[7]
PA_BUF_LT[1]
PART_NUM[7]
ED_LEVEL[7]
RX_PDT_DIS
AVREG_EXT
MAN_ID_0[7]
MAN_ID_1[7]
PAN_ID_0[7]
PAN_ID_1[7]
CCA_DONE
PA_EXT_EN
FTN_START
PAD_IO[1]
BAT_LOW
ANT_SEL
Bit7
-
-
-
-
-
-
-
-
-
The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and
monitor the radio transceiver.
Note:
MAX_FRAME_RETRES[2]
SHORT_ADDR_0[6]
SHORT_ADDR_1[6]
VERSION_NUM[6]
TRAC_STATUS[1]
IEEE_ADDR_0[6]
IEEE_ADDR_1[6]
IEEE_ADDR_2[6]
IEEE_ADDR_3[6]
IEEE_ADDR_4[6]
IEEE_ADDR_5[6]
IEEE_ADDR_6[6]
IEEE_ADDR_7[6]
MASK_TRX_UR
IRQ_2_EXT_EN
RND_VALUE[1]
CCA_MODE[1]
SFD_VALUE[6]
XTAL_MODE[2]
PA_BUF_LT[0]
PART_NUM[6]
CCA_STATUS
ED_LEVEL[6]
MAN_ID_0[6]
MAN_ID_1[6]
PAN_ID_0[6]
PAN_ID_1[6]
PAD_IO[0]
AVDD_OK
TRX_UR
Bit6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
All registers not mentioned within the following table are reserved for internal use and must not be
overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset
value.
MAX_FRAME_RETRES[1]
AACK_FLTR_RES_FT
TX_AUTO_CRC_ON
SHORT_ADDR_0[5]
SHORT_ADDR_1[5]
VERSION_NUM[5]
TRAC_STATUS[0]
PAD_IO_CLKM[1]
IEEE_ADDR_0[5]
IEEE_ADDR_1[5]
IEEE_ADDR_2[5]
IEEE_ADDR_3[5]
IEEE_ADDR_4[5]
IEEE_ADDR_5[5]
IEEE_ADDR_6[5]
IEEE_ADDR_7[5]
RND_VALUE[0]
CCA_MODE[0]
SFD_VALUE[5]
XTAL_MODE[1]
PART_NUM[5]
ED_LEVEL[5]
BATMON_OK
MAN_ID_0[5]
MAN_ID_1[5]
PAN_ID_0[5]
PAN_ID_1[5]
MASK_AMI
PA_LT[1]
Bit5
AMI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX_FRAME_RETRES[0]
MASK_CCA_ED_DONE
AACK_UPLD_RES_FT
SHORT_ADDR_0[4]
SHORT_ADDR_1[4]
VERSION_NUM[4]
PAD_IO_CLKM[0]
IEEE_ADDR_0[4]
IEEE_ADDR_1[4]
IEEE_ADDR_2[4]
IEEE_ADDR_3[4]
IEEE_ADDR_4[4]
IEEE_ADDR_5[4]
IEEE_ADDR_6[4]
IEEE_ADDR_7[4]
TRX_STATUS[4]
CCA_ED_DONE
SFD_VALUE[4]
XTAL_MODE[0]
PART_NUM[4]
RX_BL_CTRL
ED_LEVEL[4]
BATMON_HR
TRX_CMD[4]
CHANNEL[4]
MAN_ID_0[4]
MAN_ID_1[4]
PAN_ID_0[4]
PAN_ID_1[4]
PA_LT[0]
RSSI[4]
Bit4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX_CSMA_RETRES[2]
SPI_CMD_MODE[1]
CCA_ED_THRES[3]
SHORT_ADDR_0[3]
SHORT_ADDR_1[3]
RX_PDT_LEVEL[3]
VERSION_NUM[3]
CLKM_SHA_SEL
MASK_TRX_END
BATMON_VTH[3]
IEEE_ADDR_0[3]
IEEE_ADDR_1[3]
IEEE_ADDR_2[3]
IEEE_ADDR_3[3]
IEEE_ADDR_4[3]
IEEE_ADDR_5[3]
IEEE_ADDR_6[3]
IEEE_ADDR_7[3]
TRX_STATUS[3]
PDT_THRES[3]
SFD_VALUE[3]
XTAL_TRIM[3]
PART_NUM[3]
TRX_CMD[3]
ED_LEVEL[3]
ANT_DIV_EN
DVREG_EXT
MAN_ID_0[3]
MAN_ID_1[3]
CHANNEL[3]
PAN_ID_0[3]
PAN_ID_1[3]
TX_PWR[3]
TRX_END
RSSI[3]
Bit3
-
-
-
-
-
-
-
-
-
-
MAX_CSMA_RETRES[1]
SPI_CMD_MODE[0]
CCA_ED_THRES[2]
SHORT_ADDR_0[2]
SHORT_ADDR_1[2]
MASK_TRX_START
ANT_EXT_SW_EN
RX_PDT_LEVEL[2]
AACK_ACK_TIME
VERSION_NUM[2]
BATMON_VTH[2]
IEEE_ADDR_0[2]
IEEE_ADDR_1[2]
IEEE_ADDR_2[2]
IEEE_ADDR_3[2]
IEEE_ADDR_4[2]
IEEE_ADDR_5[2]
IEEE_ADDR_6[2]
IEEE_ADDR_7[2]
TRX_STATUS[2]
CLKM_CTRL[2]
PDT_THRES[2]
SFD_VALUE[2]
XTAL_TRIM[2]
PART_NUM[2]
ED_LEVEL[2]
TRX_CMD[2]
CHANNEL[2]
MAN_ID_0[2]
MAN_ID_1[2]
PAN_ID_0[2]
PAN_ID_1[2]
TX_PWR[2]
RX_START
DVDD_OK
RSSI[2]
Bit2
-
-
-
-
-
-
-
-
-
MAX_CSMA_RETRES[0]
OQPSK_DATA_RATE[1]
MASK_PLL_UNLOCK
AACK_PROM_MODE
CCA_ED_THRES[1]
SHORT_ADDR_0[1]
SHORT_ADDR_1[1]
IRQ_MASK_MODE
RX_PDT_LEVEL[1]
VERSION_NUM[1]
BATMON_VTH[1]
IEEE_ADDR_0[1]
IEEE_ADDR_1[1]
IEEE_ADDR_2[1]
IEEE_ADDR_3[1]
IEEE_ADDR_4[1]
IEEE_ADDR_5[1]
IEEE_ADDR_6[1]
IEEE_ADDR_7[1]
TRX_STATUS[1]
CLKM_CTRL[1]
PDT_THRES[1]
SFD_VALUE[1]
PLL_UNLOCK
XTAL_TRIM[1]
PART_NUM[1]
ED_LEVEL[1]
ANT_CTRL[1]
TRX_CMD[1]
CHANNEL[1]
MAN_ID_0[1]
MAN_ID_1[1]
PAN_ID_0[1]
PAN_ID_1[1]
TX_PWR[1]
RSSI[1]
Bit1
-
-
-
-
-
-
-
-
-
AT86RF231
OQPSK_DATA_RATE[0]
SLOTTED_OPERATION
CCA_ED_THRES[0]
SHORT_ADDR_0[0]
SHORT_ADDR_1[0]
RX_PDT_LEVEL[0]
MASK_PLL_LOCK
VERSION_NUM[0]
BATMON_VTH[0]
IEEE_ADDR_3[0]
IEEE_ADDR_4[0]
IEEE_ADDR_5[0]
IEEE_ADDR_6[0]
IEEE_ADDR_7[0]
TRX_STATUS[0]
IEEE_ADDR_0[0]
IEEE_ADDR_1[0]
IEEE_ADDR_2[0]
IRQ_POLARITY
CLKM_CTRL[0]
PDT_THRES[0]
SFD_VALUE[0]
XTAL_TRIM[0]
PART_NUM[0]
ED_LEVEL[0]
ANT_CTRL[0]
TRX_CMD[0]
CHANNEL[0]
MAN_ID_0[0]
MAN_ID_1[0]
PAN_ID_0[0]
PAN_ID_1[0]
TX_PWR[0]
PLL_LOCK
RSSI[0]
Bit0
-
-
-
-
-
-
-
-
-
-
24,30,148
169
44,68,97
33,44,68
90,136
68,140
8,118,
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