ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 67

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

7.2.5
8111C–MCU Wireless–09/09
Interrupt Handling
or TRAC_STATUS = SUCCESS_DATA_PENDING if the frame pending subfield of the received
ACK frame was set to 1.
The interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode,
refer to
setting the appropriate bit in register 0x0E (IRQ_MASK).
For RX_AACK and TX_ARET the following interrupts inform about the status of a frame recep-
tion and transmission:
Table 7-13.
RX_AACK
For RX_AACK it is recommended to enable IRQ_3 (TRX_END). This interrupt is issued only if a
frame passes the frame filtering, refer to
valid FCS. This is in contrast to Basic Operating Mode, refer to
on page
On reception of a valid PHR an IRQ_2 (RX_START) is issued. IRQ_5 (AMI) indicates address
match, refer to filter rules in
a frame reception with a valid FCS is indicated by interrupt IRQ_3 (TRX_END).
Thus, it can happen that an IRQ_2 (RX_START) and/or IRQ_5 (AMI) are issued, but no IRQ_3
(TRX_END) interrupt.
TX_ARET
In TX_ARET interrupt IRQ_3 (TRX_END) is only issued after completing the entire TX_ARET
transaction.
Acknowledgement frames do not issue IRQ_5 (AMI) or IRQ_3 (TRX_END) interrupts.
All other interrupts as described in
Extended Operating Mode.
Mode
RX_AACK
TX_ARET
Both
Section 7.1.3 “Interrupt Handling” on page
38. The use of the other interrupts is optional.
Interrupt
IRQ_2 (RX_START)
IRQ_5 (AMI)
IRQ_3 (TRX_END)
IRQ_3 (TRX_END)
IRQ_0 (PLL_LOCK)
Interrupt Handling in Extended Operating Mode
Section 7.2.3.5 “Frame Filtering” on page
Description
Indicates a PHR reception
Issued at address match
Signals completion of RX_AACK transaction if successful
-
-
Signals completion of TX_ARET transaction
Entering RX_AACK_ON or TX_ARET_ON state from
TRX_OFF state, the PLL_LOCK interrupt signals that the
transaction can be started
Section 6.6 “Interrupt Logic” on page
A received frame must pass the address filter
The FCS is valid
Section 7.2.3.5 “Frame Filtering” on page 61
38. The microcontroller enables interrupts by
Section 7.1.3 “Interrupt Handling”
61, and the completion of
29, are also available in
AT86RF231
and has a
67