ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 72

• Manufacturer Part Number: ATmega1284PR231
• Manufacturer: Atmel Corporation

Specifications of ATmega1284PR231

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 2
• Antenna Diversity: Yes
• External Pa Control: Yes
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 13.2
• Transmit Current Consumption (ma): 14.4
• Link Budget (dbm): 104

AT86RF231
• Bit 5 - AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1 reserved frame types are filtered similar to data frames as speci-
fied in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4, section
7.2.1.1.1.
If AACK_FLTR_RES_FT = 0 the received reserved frame is only checked for a valid FCS.
• Bit 4 - AACK_UPLD_RES_FT
If AACK_UPLD_RES_FT = 1 received frames indicated as a reserved frame are further pro-
cessed. For those frames, an IRQ_3 (TRX_END) interrupt is generated if the FCS is valid.
In conjunction with the configuration bit AACK_FLTR_RES_FT set, these frames are handled
like IEEE 802.15.4 compliant data frames during RX_AACK transaction. An IRQ_5 (AMI) inter-
rupt is issued, if the addresses in the received frame match the node's addresses.
That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is
generated and transmitted if it was requested by the received frame. If this is not wanted register
bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) has to be set.
• Bit 3 - Reserved
• Bit 2 - AACK_ACK_TIME
According to IEEE 802.15.4, section 7.5.6.4.2, the transmission of an acknowledgment frame
shall commence 12 symbols (aTurnaroundTime) after the reception of the last symbol of a data
or MAC command frame. This is achieved with the reset value of the register bit
AACK_ACK_TIME.
Alternatively, if AACK_ACK_TIME = 1 an acknowledgment frame is sent already 2 symbol peri-
ods after the reception of the last symbol of a data or MAC command frame. This may be
applied to proprietary networks or networks using the High Data Rate Modes to increase battery
lifetime and to improve the overall data throughput; refer to
Section 11.3 “High Data Rate
Modes” on page
137.
This setting affects also to acknowledgment frame response time for slotted acknowledgement
operation, see
Section 7.2.3.6 “RX_AACK Slotted Operation - Slotted Acknowledgement” on
page
62.
• Bit 1 - AACK_PROM_MODE
Register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode;
refer to IEEE 802.15.4-2006, section 7.5.6.5.
If this bit is set, every incoming frame with a valid PHR finishes with IRQ_3 (TRX_END) interrupt
even if the third level filter rules do not match or the FCS is not valid. Register bit
RX_CRC_VALID (register 0x06, PHY_RSSI) is set accordingly.
Here, if a frame passes the third level filter rules, an acknowledgement frame is generated and
transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1).
• Bit 0 - Reserved
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8111C–MCU Wireless–09/09