ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet - Page 136

• Manufacturer Part Number: ATmega1284RZAP
• Manufacturer: Atmel Corporation

Specifications of ATmega1284RZAP

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

14.11.7
14.11.8
8059D–AVR–11/09
ICRnH and ICRnL – Input Capture Register n
TIMSK1 – Timer/Counter1 Interrupt Mask Register
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7:6 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 59) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4:3 – Res: Reserved Bits
These bits are unused bits in the ATmega1284P, and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See Section “9.3” on page
Bit
Read/Write
Initial Value
Bit
(0x6F)
Read/Write
Initial Value
See Section “14.3” on page 112.
R/W
R
7
0
7
–
0
R/W
R
6
–
0
6
0
53.) is executed when the TOV1 Flag, located in TIFR1, is set.
ICIE1
R/W
R/W
5
0
5
0
R/W
R
4
–
0
4
0
ICRn[15:8]
ICRn[7:0]
R/W
R
3
–
0
3
0
OCIE1B
R/W
R/W
2
0
2
0
ATmega1284P
OCIE1A
R/W
R/W
1
0
1
0
TOIE1
R/W
R/W
0
0
0
0
TIMSK1
ICRnH
ICRnL
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