ATmega1284RZAP Atmel Corporation, ATmega1284RZAP Datasheet - Page 271

• Manufacturer Part Number: ATmega1284RZAP
• Manufacturer: Atmel Corporation

Specifications of ATmega1284RZAP

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 20 MHz
• Max I/o Pins: 32
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: No
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 3
• Frequency Band: 2.4 GHz
• Max Data Rate (mb/s): 0.25
• Antenna Diversity: No
• External Pa Control: No
• Power Output (dbm): 3
• Receiver Sensitivity (dbm): -101
• Receive Current Consumption (ma): 16.0
• Transmit Current Consumption (ma): 17.0
• Link Budget (dbm): 104

23.5.2
8059D–AVR–11/09
Scanning the RESET Pin
Figure 23-4. General Port Pin Schematic Diagram
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
inserted for the 5V reset signal.
Figure 23-5. Observe-only Cell
See Boundary-scan
Description for Details!
Pxn
From System Pin
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
IDxn
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
Previous
From
PUExn
Cell
ShiftDR
0
1
ClockDR
SLEEP
OCxn
ODxn
D
FF1
SYNCHRONIZER
WDx:
RDx:
WRx:
RRx:
RPx:
CLK
D
L
Q
Q
Q
Next
I/O
Cell
To
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
Q
Q
To System Logic
RESET
RESET
Q
Q
Q
Q
PORTxn
ATmega1284P
DDxn
CLR
CLR
D
D
CLK
PUD
WDx
RDx
WRx
RPx
RRx
I/O
Figure 23-5
271
is