ATmega162 Atmel Corporation, ATmega162 Datasheet
ATmega162
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ATmega162 Summary of contents
Page 1
... PDIP, 44-lead TQFP, and 44-pad MLF • Operating Voltages – 1.8 - 5.5V for ATmega162V – 2.7 - 5.5V for ATmega162 • Speed Grades – MHz for ATmega162V (see – MHz for ATmega162 (see ® 8-bit Microcontroller (1) Figure 113 on page 266) Figure 114 on page 266) ...
Page 2
... Pin Figure 1. Pinout ATmega162 Configurations Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega162/V 2 PDIP (OC0/T0) PB0 1 (OC2/T1) PB1 2 (RXD1/AIN0) PB2 ...
Page 3
... Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2 ...
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... Atmel ATmega162 is a powerful microcontroller that provides a highly flexi- ble and cost effective solution to many embedded control applications. The ATmega162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits ...
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... When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega162 as listed on 72. Port B (PB7..PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
Page 6
... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega162 as listed on 78. Port E(PE2..PE0) Port 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 2513K–AVR–07/09 1. ATmega162/V 7 ...
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... These code examples assume that the part specific header file is included before Examples compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C compiler documen- tation for more details. ATmega162/V 8 2513K–AVR–07/09 ...
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... Space addressing – enabling efficient address calculations. One of the these address pointers 2513K–AVR–07/09 Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega162/V Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit ...
Page 10
... The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value ATmega162 ...
Page 11
... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 2513K–AVR–07/09 ⊕ V ATmega162/V 11 ...
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... Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. ATmega162/V 12 shows the structure of the 32 general purpose working registers in the CPU. ...
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... SP15 SP14 SP13 SP12 SP11 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R ATmega162/V Figure R26 (0x1A R28 (0x1C R30 (0x1E SP10 SP9 SP8 SPH SP3 SP2 SP1 SP0 SPL R/W ...
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... The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to information. The Reset Vector can also be moved to the start of the Boot Flash section by pro- ATmega162 directly generated from the selected clock source for the ...
Page 15
... EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ 2513K–AVR–07/09 “Boot Loader Support – Read-While-Write Self- 217. ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) /* store SREG value */ ATmega162/V 15 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATmega162 set global interrupt enable 2513K–AVR–07/09 ...
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... Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega162 Program Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “ ...
Page 18
... Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the ATmega162 is in the ATmega161 compatibility mode. ...
Page 19
... SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega162 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles ...
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... Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega162 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
Page 21
... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATmega162 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt ...
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... The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 1. EEPROM Programming Time Symbol EEPROM write (from CPU) Note: ATmega162/V 22 Number of Calibrated RC Oscillator Cycles 1. Uses 1 MHz clock, independent of CKSEL Fuse settings Table 1 lists the typical pro- ...
Page 23
... Write logical one to E?MWE sbi EECR,EEMWE ; Start eeprom write by ?etting EEWE sbi EECR,EEWE ret /* Wait for complet?on of previous write */ while(EECR & (1<<EEWE Set up address and da?a registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical on? to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by?setting EEWE */ EECR |= (1<<EEWE); ATmega162/V 23 ...
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... Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V can be used Reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. ATmega162/V 24 EEARH, r18 EEARL, r17 ...
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... I/O Memory The I/O space definition of the ATmega162 is shown in All ATmega162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... AD7:0: Multiplexed low-order address bus and data bus • A15:8: High-order address bus (configurable number of bits) • ALE: Address latch enable • RD: Read strobe. • WR: Write strobe. ATmega162/V 26 70, Table 35 on page 75, and Table 41 on page Figure 11. Internal Memory External Memory (0-64K ...
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... PCB wiring delay (dependent on the capacitive load). AVLLC AD7:0 D ALE G AVR A15 ATmega162/V 63. The XMEM interface will autodetect Figure 13 (this figure shows in Table 114 to Table 121 on page ) must not exceed su D[7:0] A[7:0] ...
Page 28
... The most important parameters are the access time for the external memory in conjunc- tion with the set-up requirement of the ATmega162. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actu- ally is driven on the bus ...
Page 29
... DA7:0 (XMBK = 1) Prev. data Address RD 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external). ATmega162 Address XX Data Data Data ...
Page 30
... The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits. ATmega162 ...
Page 31
... Wait two cycles during read/write and wait one cycle before driving out 1 new address (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see 13 to Figure 16 how the setting of the SRW bits affects the timing. ATmega162/V Wait-states Figure 31 ...
Page 32
... Addressing above address 0x84FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Applica- tion software, the external 32 KB memory will appear as one linear 32 KB address space from 0x0500 to 0x84FF. This is illustrated in ATmega161 compatibility mode, configuration A to the non-compatible mode. ATmega162 ...
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... Memory 0x84FF 0x8500 (Unused) 0xFFFF 2513K–AVR–07/09 External 32K SRAM 0x0000 0x0000 0x045F 0x0460 0x04FF 0x0500 0x7FFF 0x7FFF 0x8000 0x845F 0x8460 0xFFFF ATmega162/V Memory Configuration B AVR Memory Map External 32K SRAM Internal Memory External Memory (Unused) 0x0000 0x045F 0x0460 0x7FFF 33 ...
Page 34
... DDRC = 0xFF; PORTC = 0x00; SFIOR = (1<<XMM1) | (1<<XMM0 0xaa; SFIOR = 0x00 0x55; } Note: Care must be exercised using this option as most of the memory is masked away. ATmega162/V 34 (1) r16, 0xFF DDRC, r16 r16, 0x00 PORTC, r16 r16, (1<<XMM1)|(1<<XMM0) SFIOR, r16 r16, 0xaa 0x0001+OFFSET, r16 r16, (0< ...
Page 35
... General I/O Timer/Counter Modules clk AVR Clock I/O Control Unit clk ASY System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator ATmega162/V CPU Core RAM clk CPU clk FLASH Reset Logic Watchdog Timer Source clock Watchdog clock Watchdog Oscillator Crystal Low-frequency Oscillator Crystal Oscillator “ ...
Page 36
... Typ Time-out ( Table 7. For ceramic resonators, the capacitor values given by the CKSEL3..0 1111 - 1000 0111 - 0100 0010 0000 0011, 0001 “ATmega162 Typi- = 3.0V) Number of Cycles CC 4 (4,096 64K (65,536) Figure 19. Either a quartz crystal or a Table 6. 2513K–AVR–07/09 ...
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... 16K CK 10 16K CK 11 16K CK ATmega162/V XTAL2 XTAL1 GND Table Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – Additional Delay from Recommended Reset (V = 5.0V) Usage CC 4.1 ms Ceramic resonator, ...
Page 38
... V chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset ATmega162 These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application ...
Page 39
... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in the ATmega162, and will always read as zero. • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process vari- ations from the Oscillator frequency ...
Page 40
... When the CKOUT Fuse is programmed, the system clock will be output on PortB 0. This mode is suitable when chip clock is used to drive other circuits on the system. The clock will be output buffer also during Reset and the normal operation of PortB will be overridden when the fuse is pro- ATmega162/V 40 Min Frequency in Percentage of Nominal Frequency ...
Page 41
... The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. System Clock The ATmega162 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease the system clock frequency and power consumption when Prescaler the requirement for processing power is low ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 15. Clock Prescaler Select CLKPS3 ATmega162/V 42 CLKPS2 CLKPS1 CLKPS0 ...
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... Read/Write Initial Value • Bit 5 – SM2: Sleep Mode Select Bit 2 The Sleep Mode Select bits select between the five available sleep modes as shown in 16. 2513K–AVR–07/09 presents the different clock systems in the ATmega162, and their distribu SRE ...
Page 44
... When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ATmega162 ...
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... Oscillators Main Clock Timer Osc clk clk Source Enabled Enabled IO ASY ( ( ATmega162/V , allowing operation only of asynchronous ASY Wake-up Sources INT2 INT1 INT0 EEPROM 2 and Pin Change Timer ( (3) X (2) (3) ( (3) X ...
Page 46
... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. ATmega162/V 46 “Analog Comparator” on page 195 “ ...
Page 47
... CKSEL Fuses. The different selections for the delay period are presented in Reset Sources The ATmega162 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
Page 48
... POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V CC ATmega162/V 48 Power- Reset Circuit Brown-out ...
Page 49
... V POT RST RESET t TOUT RESET V POT V CC RESET RESET Table 18) will generate a Reset, even if the clock is not running. on its positive edge, the delay counter starts the MCU after the RST has expired. TOUT CC ATmega162 RST t TOUT 49 ...
Page 50
... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. This test is performed using BODLEVEL = 110 for ATmega162V, BODLEVEL = 101 and BODLEVEL = 100 for ATmega162. 2. For ATmega162V. Otherwise reserved. Parameter ...
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... BOT- RESET RESET for details on operation of the Watchdog Timer JTD – SM2 JTRF R/W R ATmega162/V V BOT+ t TOUT WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description . Refer to TOUT 51 ...
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... Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega162 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3 different safety levels are selected by the Fuses M161C and WDTON as shown in Table 22 ...
Page 53
... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega162 and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
Page 54
... Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 23. Watchdog Timer Prescale Select WDP2 ATmega162/V 54 See “Timed Sequences for Changing the Configuration of the Watchdog Table 23. Number of WDT WDP1 WDP0 Oscillator Cycles 0 0 16K (16,384) ...
Page 55
... Write logical one to W?CE and WDE in r16, WDTCR ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret /* Reset WDT*/ _WDR() /* Write logical on? to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<?WDE); /* Turn off WDT */ WDTCR = 0x00; ATmega162/V 55 ...
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... WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. ATmega162/V 56 page 53 (WDE bit description) must be followed. ...
Page 57
... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega162. For a general explanation of the AVR interrupt handling, refer to page 14. grammed, while assembly code examples in this sections are using the interrupt table when the M161C Fuse is unprogrammed. Interrupt Vectors Table 24. Reset and Interrupt Vectors if M161C is unprogrammed in ATmega162 Vector No ...
Page 58
... Notes: ATmega162 When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-programming” on page 2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the Boot Flash section ...
Page 59
... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 26. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega162 is: Address 0x000 0x002 0x004 0x006 0x008 0x00A 0x00C 0x00E ...
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... Reset and Interrupt Vector Addresses is: Address .org 0x002 0x002 0x004 ... 0x036 ; .org 0x1C00 0x1C00 0x1C01 0x1C02 0x1C03 0x1C04 0x1C05 ATmega162/V 60 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ... ... Labels Code RESET: ldi r16,high(RAMEND) ; Main program start ...
Page 61
... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Write Self-programming” on page 217 ATmega162/V Comments ; Reset handler ; IRQ0 Handler ...
Page 62
... Enable change of Inter?upt Vectors ldi out ; Move interrupts to Boo? Flash section ldi out ret C Code Example void Move_interrupts(void Enable change of?Interrupt Vectors */ GICR = (1<<IVCE); /* Move interrupts to Bo?t Flash section */ GICR = (1<<IVSEL); } ATmega162/V 62 r16, (1<<IVCE) GICR, r16 r16, (1<<IVSEL) GICR, r16 2513K–AVR–07/09 ...
Page 63
... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description for I/O-Ports” on page 68. Refer to the individual module sections for a full description of the alter- ATmega162/V Figure 28. Refer to “Electrical Charac Logic See figure "General Digital I/O" for details 82 ...
Page 64
... PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept- able high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. ATmega162/V 64 (1) Pxn ...
Page 65
... X Output Figure 29, the PINxn Register bit and the preceding latch consti- and t pd,max SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATmega162/V Pull-up Comment No Tri-state (Hi-Z) Pxn will source current if ext. pulled Yes low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...
Page 66
... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in clock. In this case, the delay t Figure 31. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS ATmega162/V 66 and single signal transition on the pin will be delayed pd,max pd,min Figure 31. The out instruction sets the “ ...
Page 67
... Figure 29, the digital input signal can be clamped to ground at the input of the /2. CC ATmega162/V “Alternate Port Functions” on page 68. 67 ...
Page 68
... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 32. Alternate Port Functions Note: ATmega162 GND is not recommended, since this may cause excessive currents if the pin is CC ...
Page 69
... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. Analog This is the Analog Input/output to/from alternate functions. Input/output The signal is connected directly to the pad, and can be used bi-directionally. ATmega162/V Fig- 69 ...
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... Port A has an alternate function as the address low byte and data lines for the External Memory Port A Interface and as Pin Change Interrupt. Table 29. Port A Pins Alternate Functions Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Table 30 Figure 32 on page ATmega162 TSM XMBK XMM2 XMM1 R/W R/W R/W R/W 0 ...
Page 71
... PCIE0 • PCINT3 PCIE0 • PCINT2 INPUT D2 INPUT /PCINT3 /PCINT2 – – 1. PCINT is Pin Change Interrupt Enable bit n. 2. PCINT is Pin Change Interrupt input n. ATmega162/V PA5/AD5/PCINT5 PA4/AD4/PCINT4 SRE SRE ~(WR + ADA) • ~(WR + ADA) • PORTA5 PORTA4 SRE SRE WR + ADA WR + ADA SRE ...
Page 72
... OC3B, Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. ATmega162/V 72 Alternate Functions ...
Page 73
... Figure 32 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 2513K–AVR–07/09 and Table 34 relate the alternate functions of Port B to the overriding signals shown in 68. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, ATmega162/V 73 ...
Page 74
... Table 34. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: ATmega162/V 74 PB7/SCK PB6/MISO SPE • MSTR SPE • MSTR PORTB7 • PORTB6 • PUD PUD SPE • MSTR SPE • MSTR 0 0 SPE • ...
Page 75
... PCINT11 (Pin Change INTerrupt 11) A10 (External memory interface address bit 10) PCINT10 (Pin Change INTerrupt 10) A9 (External memory interface address bit 9) PCINT9 (Pin Change INTerrupt 9) A8 (External memory interface address bit 8) PCINT8 (Pin Change INTerrupt 8) ATmega162/V Table 35. If the JTAG interface is enabled, 75 ...
Page 76
... PCINT9: The pin can also serve as a pin change interrupt. • A8/PCINT8 – Port C, Bit 0 A8, External memory interface address bit 8. PCINT8: The pin can also serve as a pin change interrupt. Table 36 Figure 32 on page ATmega162/V 76 and Table 37 relate the alternate functions of Port C to the overriding signals shown in 68. ...
Page 77
... PCIE1 • PCINT11 PCINT10 1 1 PCINT11 PCINT10 – – 1. PCINTn is Pin Change Interrupt Enable bit n. 2. PCINTn is Pin Change Interrupt input n. ATmega162/V PC5/A13/TMS PC4/A12/TCK /PCINT13 /PCINT12 (XMM < 3) • (XMM < 4) • SRE + JTAGEN SRE + JTAGEN JTAGEN JTAGEN SRE • (XMM<3) SRE • ...
Page 78
... OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. ATmega162/V 78 Alternate Function ...
Page 79
... The XCK1 pin is active only when USART1 operates in Synchronous mode. • TXD0 – Port D, Bit 1 TXD0, Transmit Data (Data output pin for USART0). When the USART0 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. 2513K–AVR–07/09 ATmega162/V 79 ...
Page 80
... DI AIO Table 40. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega162/V 80 and Table 40 relate the alternate functions of Port D to the overriding signals shown in 68. PD7/RD PD6/WR PD5/TOSC2/OC1A SRE SRE AS2 ...
Page 81
... ALE (Address Latch Enable to external memory) ICP1 (Timer/Counter1 Input Capture Pin) INT2 (External Interrupt 2 Input) relate the alternate functions of Port E to the overriding signals shown in PE2 OC1B ENABLE OC1B – ATmega162/V Table 41. Figure 32 on PE1 PE0 SRE SRE SRE ...
Page 82
... Read/Write Initial Value Port B Input Pins Bit Address – PINB Read/Write Initial Value Port C Data Register – Bit PORTC Read/Write Initial Value Port C Data Direction Bit Register – DDRC Read/Write Initial Value ATmega162 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 R/W R/W R/W R ...
Page 83
... – – – – – – – – ATmega162 PINC3 PINC2 PINC1 PINC0 N/A N/A N/A N PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 ...
Page 84
... Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. ATmega162/V 84 “Clock Systems and their Distribution” on page “Electrical Characteristics” on page 35 ...
Page 85
... The rising edge of INT0 generates an interrupt request SM0 SRL2 SRL1 SRL0 R/W R/W R/W R Table 45 will generate an interrupt. Shorter pulses are not guaranteed to generate Parameter Minimum pulse width for asynchronous external interrupt ATmega162 SRW01 SRW00 SRW11 ISC2 EMCUCR R/W R/W R/W R Condition Min. Typ. Max. ...
Page 86
... When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. ATmega162 ...
Page 87
... Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 2513K–AVR–07/ INTF1 INTF0 INTF2 PCIF1 PCIF0 R/W R/W R/W R for more information. ATmega162 – – – GIFR R “Digital Input Enable and Sleep 87 ...
Page 88
... I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. The mapping between I/O pins and PCINT bits can be found in Pin Change Mask Register are located in Extended I/O. Thus, the pin change interrupts are not supported in ATmega161 compatibility mode. ATmega162 ...
Page 89
... The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk 2513K–AVR–07/09 “Pinout ATmega162” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...
Page 90
... Clock Select logic which is controlled by the Clock Select (CS02:0) bits Clock Sources located in the Timer/Counter Control Register (TCCR0). For details on clock sources and pres- caler, see ATmega162/V 90 for details. The Compare Match event will also set the Compare Flag Table 46 are also used extensively throughout the document ...
Page 91
... present or not. A CPU write overrides (has priority over) all counter clear or T 94. (See “Modes of Operation” on page shows a block diagram of the output compare unit. ATmega162/V TOVn (Int.Req.) Clock Select Edge Detector clk Tn ...
Page 92
... All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the Blocking by TCNT0 next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized Write to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. ATmega162/V 92 DATA BUS OCRn = (8-bit Comparator ) ...
Page 93
... OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the pin. The port override function is independent of the Waveform Generation mode. 2513K–AVR–07/09 COMn1 Waveform COMn0 Generator FOCn clk I/O ATmega162/V Figure 36 shows a simplified sche OCn ...
Page 94
... The timing diagram for the CTC mode is shown in increases until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared. ATmega162/V 94 See “8-bit Timer/Counter Register Description” on page 100. Table 48 on page 101 ...
Page 95
... PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. 2513K–AVR–07/ clk_I ---------------------------------------------- - OCn ⋅ ⋅ OCRn 1 Figure 38. The TCNT0 value is in the timing diagram shown as a histo- ATmega162/V OCn Interrupt Flag Set (COMn1 clk_I ...
Page 96
... The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non- inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while up-counting, and set on the Compare Match while down- counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation ATmega162/V 96 TCNTn OCn ...
Page 97
... The PWM frequency for the output when using phase correct PWM can be calculated by the fol- lowing equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). 2513K–AVR–07/ clk_I ----------------- - OCnPCPWM ⋅ N 510 ATmega162/V Figure 39. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 Table 50 on page 101). The 97 ...
Page 98
... TCNTn TOVn Figure 41 Figure 41. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 42 ATmega162/V 98 Figure 39 OCn has a transition from high to low even though there Figure 40 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ...
Page 99
... Figure 43. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn 2513K–AVR–07/09 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. /8) I/O Tn /8) I/O TOP - 1 ATmega162/V OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 99 ...
Page 100
... These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0 pin must be set in order to enable the output driver. ATmega162/V 100 7 6 ...
Page 101
... Compare Match when down-counting special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See 96 for more details. ATmega162/V (1) “Fast PWM Mode” on page 95 (1) “Phase Correct PWM Mode” on page ...
Page 102
... When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. ATmega162/V 102 CS01 CS00 ...
Page 103
... In ATmega161 OCIE2 TOIE2 have switched places in the TIMSK register. and TOV1 OCF1A OCF1B OCF2 R/W R/W R/W R ATmega161 OCF2 TOV2 have switched places in the TIFR register. and ATmega162 ICF1 TOV2 TOV0 OCF0 R/W R/W R/W R TIFR 103 ...
Page 104
... Tn/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. ATmega162/V 104 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O 0) for Timer/Counter1 and Timer/Counter0 ...
Page 105
... CS11 CS32 CS12 TIMER/COUNTER3 CLOCK SOURCE clk T3 1. The synchronization logic on the input pins ( TSM XMBK XMM2 XMM1 R/W R/W R/W R ATmega162/V 10-BIT T/C PRESCALER Clear CS00 CS01 CS02 TIMER/COUNTER1 CLOCK SOURCE TIMER/COUNTER1 CLOCK SOURCE clk T1 Tn/T0) is shown in Figure XMM0 ...
Page 106
... I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the ATmega162/V 106 “Pinout ATmega162” on page “16-bit Timer/Counter Register Description” on page Figure 46. For the actual 2. CPU accessible I/O Registers, 128. ...
Page 107
... Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA 1. Refer to Figure 1 on page 2, Timer/Counter1 pin placement and description. The Compare Match event will also set the Compare Match ATmega162/V (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int ...
Page 108
... WGMn3 is added to TCCRnB. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. ATmega162/V 108 195.) The Input Capture unit includes a digital filtering unit (Noise The counter reaches the BOTTOM when it becomes 0x0000. The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535) ...
Page 109
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega162/V 109 ...
Page 110
... Read TCNTn into TCNTn; /* Restore Global I?terrupt Flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNTn value in the r17:r16 register pair. ATmega162/V 110 (1) r18,SREG r16,TCNTnL r17,TCNTnH (1) 1. The example code assumes that the part specific header file is included. ...
Page 111
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega162/V 111 ...
Page 112
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see ATmega162/V 112 shows a block diagram of the counter and its surroundings. ...
Page 113
... ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn 1. The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3. ATmega162/V Figure (1) DATA BUS (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise ...
Page 114
... Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Com- pare Flag generates an output compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writ- ATmega162/V 114 109. “Accessing 16-bit Registers” ...
Page 115
... The small “n” in the register and bit DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega162/V 118.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 116
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. ATmega162/V 116 109. “Accessing 16-bit Registers” ...
Page 117
... Note that some COMnx1:0 bit settings are reserved for certain modes of operation. The COMnx1:0 bits have no effect on the Input Capture unit. 2513K–AVR–07/09 COMnx1 Waveform COMnx0 Generator FOCnx clk I/O See “16-bit Timer/Counter Register Description” on page 128. ATmega162/V Figure 50 shows a simplified OCnx OCnx PORT ...
Page 118
... Compare Match output frequency. It also simplifies the oper- ation of counting external events. The timing diagram for the CTC mode is shown in increases until a Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. ATmega162/V 118 Table 53 on page 128. For fast PWM mode refer to 117.) “ ...
Page 119
... MAX to 0x0000. 2513K–AVR–07/09 TCNTn OCnA (Toggle) Period when OCRnA is set to zero (0x0000). The waveform frequency clk_I OCnA ATmega162/V OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O -------------------------------------------------- - ⋅ ⋅ OCRnA ...
Page 120
... TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the com- ATmega162/V 120 ( ...
Page 121
... OCnA toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast PWM mode. 2513K–AVR–07/09 Table on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCRnA is set to zero (0x0000). This feature clk_I/O ATmega162/V 129). The actual OCnx ) 121 ...
Page 122
... The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord- ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer ATmega162/V 122 ( ...
Page 123
... The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see and Figure 2513K–AVR–07/09 f OCnxPCPWM 54). ATmega162/V Figure 53 illustrates, changing the TOP Table 55 on page f clk_I/O = --------------------------- - ⋅ ...
Page 124
... Compare Match will never occur between the TCNTn and the OCRnx. As Figure 54 in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore fre- quency correct. ATmega162/V 124 R = PFCPWM Figure 54 ...
Page 125
... PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3 and COMnA1 the OCnA output will toggle with a 50% duty cycle. 2513K–AVR–07/09 f clk_I --------------------------- - OCnxPFCPWM ⋅ ⋅ TOP ATmega162/V Table 55 on 125 ...
Page 126
... Figure 57 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. ATmega162/V 126 Figure 55 I/O Tn ...
Page 127
... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega162/V TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value ...
Page 128
... When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen- dent of the WGMn3:0 bits setting. WGMn3:0 bits are set to a normal or a CTC mode (non-PWM). Table 53. Compare Output Mode, non-PWM COMnA1/ COMnB1 ATmega162/V 128 COM1A1 COM1A0 COM1B1 COM1B0 ...
Page 129
... OCnA/OCnB on Compare Match when down-counting. 1 Set OCnA/OCnB on Compare Match when up-counting. Clear OCnA/OCnB on Compare Match when down-counting special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. “Phase Correct PWM Mode” on page 122. ATmega162/V (1) for more details. See “Fast PWM (1) See ...
Page 130
... Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega162/V 130 Table 56. Modes of operation supported by the Timer/Counter (See “Modes of Operation” on page ...
Page 131
... See TCCRnA Register description. 2513K–AVR–07/ ICNC1 ICES1 – WGM13 WGM12 R/W R ICNC3 ICES3 – WGM33 WGM32 R/W R ATmega162 CS12 CS11 CS10 TCCR1B R/W R/W R/W R CS32 CS31 CS30 TCCR3B R/W R/W R/W R 131 ...
Page 132
... If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.. Table 58. Clock Select Bit Description Timer/Counter3 CS32 ATmega162/V 132 56. CS11 CS10 Description clock source. (Timer/Counter stopped clk /1 (No prescaling) ...
Page 133
... OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R/W R OCR3A[15:8] OCR3A[7:0] R/W R/W R/W R/W R OCR3B[15:8] OCR3B[7:0] R/W R/W R/W R/W R ATmega162 TCNT1H TCNT1L R/W R/W R TCNT3H TCNT3L R/W R/W R See “Accessing 16-bit OCR1AH OCR1AL R/W R/W R ...
Page 134
... Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding ATmega162/V 134 See “Accessing 16-bit Registers” on page 109. ...
Page 135
... R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective Timer sections. ATmega162/V 57.) is executed when the OCF1B Flag, located OCIE3B TOIE3 – – ...
Page 136
... WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. ATmega162/V 136 2513K–AVR–07/09 ...
Page 137
... ICF3 OCF3A R R R/W R This register contains flag bits for several Timer/Counters, but only Timer3 bits are described in this section. The remaining bits are described in their respective Timer sections. ATmega162 OC3FB TOV3 – – R/W R ...
Page 138
... TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by ATmega162/V 138 “Pinout ATmega162” on page “8-bit Timer/Counter Register Description” on page TCCRn count clear ...
Page 139
... OCR2 Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T 152. For details on clock sources and prescaler, see 156. ATmega162/V See “Output Compare . When the AS2 I/O “Asyn- 139 ...
Page 140
... WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for han- dling the special cases of the extreme values in some modes of operation on page Figure 61 ATmega162/V 140 DATA BUS count clear ...
Page 141
... OCR2 value, the Compare Match will be missed, resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is down-counting. 2513K–AVR–07/09 DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 COMn1:0 ATmega162/V TCNTn OCFn (Int.Req.) OCxy 141 ...
Page 142
... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2 state before the out- put is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. ATmega162/V 142 Waveform Generator I/O See “ ...
Page 143
... Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 2513K–AVR–07/09 Table 61 on page 150. For fast PWM mode, refer to Table 63 on page 150. 142.). “Timer/Counter Timing Diagrams” on page ATmega162/V Table 62 on page 150, 147. 143 ...
Page 144
... The waveform generated will have a maximum frequency of f when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the counter counts from MAX to 0x00. ATmega162/V 144 TCNTn OCn (Toggle) ...
Page 145
... The TCNT2 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period set each time the counter reaches MAX. If the inter- TOV2 f OCnPWM ATmega162/V OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set (COMn1 (COMn1 Table 62 on page 150). The actual OC2 ...
Page 146
... Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to three (See ATmega162/V 146 TCNTn OCn OCn ...
Page 147
... Timer/Counter operation. The figure shows the clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 TOVn shows the same timing data, but with the prescaler enabled. ATmega162/V f clk_I/O = ----------------- - ⋅ N 510 Figure 65. When the OCR2 value is MAX the should be replaced by I/O MAX ...
Page 148
... Figure 67. Timer/Counter Timing Diagram, with Prescaler (f Figure 68 Figure 68. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f TCNTn Figure 69 Figure 69. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f clk_I/O (clk TCNTn ATmega162/V 148 clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 TOVn shows the setting of OCF2 in all modes except CTC mode. ...
Page 149
... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega162 WGM21 CS22 CS21 CS20 R/W ...
Page 150
... Table 63 PWM mode. Table 63. Compare Output Mode, Phase Correct PWM Mode COM21 Note: ATmega162/V 150 Table 61 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a COM20 Description 0 Normal port operation, OC2 disconnected. 1 Toggle OC2 on Compare Match. ...
Page 151
... clk /256 (From prescaler clk /1024 (From prescaler TCNT2[7:0] R/W R/W R/W R OCR2[7:0] R/W R/W R/W R ATmega162 TCNT2 R/W R/W R/W R OCR2 R/W R/W R/W R Table 151 ...
Page 152
... The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary stor- age register is read. ATmega162/V 152 7 6 ...
Page 153
... When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the Timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four 2513K–AVR–07/09 ATmega162/V 153 ...
Page 154
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. ATmega162/V 154 ) again becomes active, TCNT2 will read as the previous I/O ...
Page 155
... Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 2513K–AVR–07/ TOV1 OCF1A OC1FB OCF2 ICF1 R/W R/W R/W R/W R ATmega162 TOV2 TOV0 OCF0 TIFR R/W R/W R 155 ...
Page 156
... If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the chronization Mode” on page 105 ATmega162/V 156 clk I/O ...
Page 157
... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega162 and peripheral devices or between several AVR devices. The ATmega162 SPI Peripheral includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 158
... When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 65. SPI Pin Overrides Pin MOSI MISO SCK SS Note: ATmega162/V 158 MSB MASTER LSB MISO 8-BIT SHIFT REGISTER MOSI SPI SCK CLOCK GENERATOR ...
Page 159
... DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO, and DD_SCK must be replaced by the actual data direction bits for these pins. E.g., if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 2513K–AVR–07/09 ATmega162/V 159 ...
Page 160
... SPCR = (1<<SPE)|(1<<MSTR?|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission?complete */ while(!(SPSR & (1<<?PIF))) } Note: ATmega162/V 160 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 ( The example code assumes that the part specific header file is included. ...
Page 161
... Read received data and?return in r16,SPDR ret (1) /* Set MISO output, all ?thers input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception co?plete */ while(!(SPSR & (1<<?PIF))) ; /* Return data register ?/ return SPDR; 1. The example code assumes that the part specific header file is included. ATmega162/V 161 ...
Page 162
... When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. ATmega162/V 162 ...
Page 163
... Leading Edge 0 Sample 1 Setup SPR1 SPR0 ATmega162/V for an example. The CPOL functionality is summa- Trailing Edge Falling Rising and Figure 74 for an example. The CPHA func- Trailing Edge Setup Sample SCK Frequency osc osc f ...
Page 164
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega162 is also used for program memory and EEPROM down- loading or uploading. See SPI Data Register – Bit ...
Page 165
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega162/V Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 166
... Double Speed Asynchronous Communication Mode Dual USART The ATmega162 has two USARTs, USART0 and USART1. The functionality for both USARTs is described below. USART0 and USART1 have different I/O Registers as shown in 304. Note that in ATmega161 compatibility mode, the double buffering of the USART Receive Register is disabled ...
Page 167
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Figure 1 on page 2, Table 34 on page 80 for USART pin placement. ATmega162/V Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
Page 168
... The XCK pin is only active when using synchronous mode. Figure 76 Figure 76. Clock Generation Logic, Block Diagram XCK DDR_XCK Signal description: ATmega162/V 168 shows a block diagram of the clock generation logic. UBRR fosc UBRR+1 Prescaling ...
Page 169
... Equation for Calculating Baud Rate BAUD = BAUD = BAUD = 1. The baud rate is defined to be the transfer rate in bit per second (bps). System Oscillator clock frequency ATmega162/V Figure 76. Equation for Calculating (1) UBRR Value f f OSC OSC -------------------------------------- - ...
Page 170
... The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. ATmega162/V 170 Figure 76 for details. ...
Page 171
... even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity Data bit n of the character ATmega162/V FRAME [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 172
... Set baud rate */ UBRRH = (unsigned c?ar)(ubrr>>8); UBRRL = (unsigned c?ar)ubrr; /* Enable receiver ?nd transmitter */ UCSRB = (1<<RXEN)|(1<<TX?N); /* Set frame format? 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<U?BS)|(3<<UCSZ0); } Note: ATmega162/V 172 (1) UBRRH, r17 UBRRL, r16 r16, (1<<RXEN)|(1<<TXEN) UCSRB,r16 r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0) UCSRC,r16 (1) 1. See “ ...
Page 173
... Put data (r16) in?o buffer, sends the data out UDR,r16 ret (1) /* Wait for empty t?ansmit buffer */ while ( !( UCSRA & ?1<<UDRE Put data into bu?fer, sends the data */ UDR = data; 1. The example code assumes that the part specific header file is included. ATmega162/V 173 ...
Page 174
... UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty Interrupt, otherwise a new inter- rupt will occur once the interrupt routine terminates. ATmega162/V 174 (1) UCSRB,TXB8 ...
Page 175
... USART and given the function as the receiver’s serial input. The baud rate, mode of oper- Receiver ation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock. 2513K–AVR–07/09 ATmega162/V 175 ...
Page 176
... Get and return r?ceived data from buffer */ return UDR; } Note: The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. ATmega162/V 176 (1) r16, UDR ( The example code assumes that the part specific header file is included. ...
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... UCSRA; resh = UCSRB; resl = UDR error, return?- status & (1<<F?)|(1<<DOR)|(1<<UPE) ) return -1; /* Filter the 9th b?t, then return */ resh = (resh >> 1) & 0x0?; return ((resh << 8)?| resl); 1. The example code assumes that the part specific header file is included. ATmega162/V 177 ...
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... If parity check is not enabled the UPE bit will always be read zero. For compati- bility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 171 ATmega162/V 178 and “Parity Checker” on page 179. 2513K– ...
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... RxD line is idle (i.e., no communication activity). 2513K–AVR–07/09 (1) sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy? while ( UCSRA & (1<?RXC) ) dummy = UDR; 1. The example code assumes that the part specific header file is included. ATmega162/V Figure 79 179 ...
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... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the receiver only uses the first stop bit of a frame. Figure 81 the next frame. ATmega162/V 180 IDLE 0 0 ...
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... for Double Speed mode for Double Speed mode the ratio of the fastest incoming data rate that can be fast and Table 72 list the maximum receiver baud rate error that can be tolerated. Note that ATmega162/V STOP 1 (A) ( 0/1 0/1 0/1 4 ...
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... When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been ATmega162/V 182 D R ...
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... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. 2513K–AVR–07/09 ATmega162/V 183 ...
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... Set the USBS and?the UCSZ1 bit to one, and */ /* the remaining bi?s to zero. */ UCSRC = (1<<URSEL)|(1<<U?BS)|(1<<UCSZ1); ... Note: As the code examples illustrate, write accesses of the two registers are relatively unaffected of the sharing of I/O location. ATmega162/V 184 (1) (1) 1. The example code assumes that the part specific header file is included. 2513K–AVR–07/09 ...
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... Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc? /* Read UCSRC ?/ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. The example code assumes that the part specific header file is included. ATmega162/V 185 ...
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... The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDRE is set after a Reset to indicate that the transmitter is ready. ATmega162/V 186 7 6 ...
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... UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set. 2513K–AVR–07/09 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN TXEN R/W R/W R/W R ATmega162/V 182 UCSZ2 RXB8 TXB8 UCSRB R/W R 187 ...
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... Must be read before reading the low bits from UDR. • Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be written before writing the low bits to UDR. ATmega162/V 188 2513K–AVR–07/09 ...
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... Asynchronous Operation 1 Synchronous Operation UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity USBS 0 1 ATmega162 USBS UCSZ1 UCSZ0 UCPOL UCSRC R/W R/W R/W R section which describes how to access this Stop Bit(s) 1-bit 2-bit “ ...
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... This bit selects between accessing the UBRRH or the UCSRC Register read as zero when reading UBRRH. The URSEL must be zero when writing the UBRRH. • Bit 14:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. ATmega162/V 190 UCSZ1 0 0 ...
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... ATmega162/V Table “Asynchronous Operational ⎞ Closest Match • – 100% ⎠ BaudRate f = 2.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7. ...
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... Max. 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% ATmega162/V 192 f = 4.0000 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0.0% 16 2.1% 34 0.0% 12 0.2% 25 0.0% 8 -3.5% 16 0.0% 6 -7. ...
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... U2X = 0 Error UBRR Error -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 1 Mbps 691.2 kbps ATmega162/V MHz f = 14.7456 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 ...
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... Max. 1 Mbps 1. UBRR = 0, Error = 0.0% ATmega162/V 194 f = 18.4320 MHz osc U2X = 0 Error UBRR Error UBRR 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – ...
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... Figure 82. BANDGAP REFERENCE ACBG 1. Refer to Figure 1 on page 2 and Table 32 on page ACD ACBG ACO ACI R/W R N/A 0 ATmega162/V (1) for Analog Comparator pin placement ACIE ACIC ACIS1 ACIS0 R/W R/W R/W R ACSR 195 ...
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... ACIS1 When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. ATmega162/V 196 Table 82. ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle. ...
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... Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. 2513K–AVR–07/09 and shows a block diagram of the JTAG interface and the On-chip Debug system. The ATmega162/V ® “IEEE 1149.1 (JTAG) Boundary-scan” on page “Program- 197 ...
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... DEVICE BOUNDARY TDI TDO TAP TCK CONTROLLER TMS INSTRUCTION REGISTER ID REGISTER M BYPASS U REGISTER X BREAKPOINT SCAN CHAIN ADDRESS DECODER ATmega162/V 198 I/O PORT 0 BOUNDARY SCAN CHAIN JTAG PROGRAMMING INTERFACE AVR CPU INTERNAL FLASH Address SCAN PC MEMORY Data CHAIN Instruction BREAKPOINT UNIT FLOW CONTROL UNIT ...
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... Figure 84. TAP Controller State Diagram 1 0 2513K–AVR–07/09 Test-Logic-Reset 0 1 Run-Test/Idle Select-DR Scan 1 Capture-DR Shift-DR Exit1-DR Pause-DR 0 Exit2-DR Update-DR 1 ATmega162/V 1 Select-IR Scan Capture- Shift- Exit1- Pause- Exit2- Update- 199 ...
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... Using the A complete description of the Boundary-scan capabilities are given in the section Boundary-scan (JTAG) Boundary-scan” on page Chain ATmega162/V 200 Figure 84 depend on the signal present on TMS (shown adjacent to each state tran- Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for five TCK clock periods ...