ATmega16M1 Automotive Atmel Corporation, ATmega16M1 Automotive Datasheet
ATmega16M1 Automotive
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ATmega16M1 Automotive Summary of contents
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Features • High Performance, Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – 1MIPS throughput ...
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Internal Calibrated RC Oscillator (8MHz) – On-chip PLL for fast PWM (32MHz, 64MHz) and CPU (16MHz) • Operating Voltage: – 2.7V - 5.5V • Extended Operating Temperature: – –40°C to +125°C • Core Speed Grade: – 8MHz ...
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Pin Configurations Figure 1-1. ATmega32/64M1 TQFP32/QFN32 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 Note: 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 ATmega16/32/64M1 TQFP32/QFN32 (7*7 mm) Package. (PCINT18/PSCIN2/OC1A/MISO_A) PD2 1 2 (PCINT9/PSCIN1/OC1B/SS_A) PC1 3 VCC 4 GND 5 (PCINT10/T0/TXCAN) PC2 6 (PCINT11/T1/RXCAN/ICP1B) PC3 7 (PCINT0/MISO/PSCOUT2A) PB0 8 On the ...
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Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 Note: Atmel ATmega16/32/64/M1/C1 4 ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package (PCINT18/OC1A/MISO_A) PD2 1 2 (PCINT9/OC1B/SS_A) PC1 3 VCC 4 GND 5 (PCINT10/T0/TXCAN) PC2 6 (PCINT11/T1/RXCAN/ICP1B) PC3 7 (PCINT0/MISO) PB0 8 On the first engineering samples ...
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Pin Descriptions : Table 1-1. QFN32 Pin Number Note: 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 Pin out description Mnemonic Type 5 GND Power 20 AGND Power 4 VCC Power 19 AVCC Power 21 AREF Power 8 PB0 I/O 9 PB1 I/O 16 ...
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Table 1-1. QFN32 Pin Number Note: Atmel ATmega16/32/64/M1/C1 6 Pin out description (Continued) Mnemonic Type 30 PC0 I/O 3 PC1 I/O 6 PC2 I/O 7 PC3 I/O 17 PC4 I/O 18 PC5 I/O 22 PC6 I/O 25 PC7 I/O 29 ...
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Table 1-1. QFN32 Pin Number Note: 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 Pin out description (Continued) Mnemonic Type 2 PD3 I/O 12 PD4 I/O 13 PD5 I/O 14 PD6 I/O 15 PD7 I/O 31 PE0 I PE1 I/O 11 PE2 ...
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Overview The ATmega16/32/64/M1/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16/32/64/M1/C1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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The ATmega16/32/64/M1/C1 provides the following features: 16K/32K/64K bytes of In-Sys- tem Programmable Flash with Read-While-Write capabilities, 512/1024/2048 bytes EEPROM, 1024/2048/4096 bytes SRAM, 27 general purpose I/O lines, 32 general purpose working reg- isters, one Motor Power Stage Controller, two flexible ...
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Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB7..PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics ...
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Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from ...
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AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access mem- ories, perform calculations, ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a sin- gle clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register ...
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Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 3.5 General Purpose Register File The Register File is optimized for the ...
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Figure 3-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displace- ment, automatic increment, and automatic decrement (see the instruction set reference for details). 3.6 Stack Pointer The Stack is mainly used for ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk the chip. No internal clock division is used. Figure 3-4 Harvard architecture and the fast-access ...
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The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 3.8.2 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is ...
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Memories This section describes the different memories in the ATmega16/32/64/M1/C1. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16/32/64/M1/C1 features an EEPROM Memory for data storage. All ...
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SRAM Data Memory Figure 4-2 The ATmega16/32/64/M1/ complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from ...
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Figure 4-3. 4.3 EEPROM Data Memory The ATmega16/32/64/M1/C1 contains 512/1024/2048 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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The EEPROM Address Registers – EEARH and EEARL Bit Read/Write Initial Value • Bits 15.11 – Reserved Bits These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero. • Bits 9..0 – EEAR10..0: EEPROM Address ...
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EEPROM is busy programming. Table 4-1. EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the ...
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When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write (unsigned int uiAddress, unsigned char ucData Atmel ATmega16/32/64/M1/ Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out ...
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execu- tion of these functions. Assembly Code Example C Code Example 4.3.5 Preventing ...
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I/O Memory The I/O space definition of the ATmega16/32/64/M1/C1 is shown in page All ATmega16/32/64/M1/C1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between ...
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System Clock 5.1 Clock Systems and their Distribution Figure 5-1 clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 5.1.4 PLL Clock – clk PLL The PLL clock allows the fast peripherals to ...
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Table 5-2. Typ Time-out (V 5.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial ...
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The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5-3. CKSEL3..1 100 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses ...
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Calibrated Internal RC Oscillator By default, the Internal RC OScillator provides an approximate 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse programmed. ...
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Oscillator Calibration Register – OSCCAL Bit Read/Write Initial Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. The ...
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Table 5-7. CKSEL 3..0 0011 RC Osc 0101 Ext Osc 0001 Ext Clk Figure 5-3. PLL Clocking System OSCCAL RC OSCILLATOR 8 MHz XTAL1 OSCILLATORS XTAL2 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 Start-up Times when the PLL is selected as ...
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PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega16/32/64/M1/C1 and always read as zero. • Bit 2 – PLLF: PLL ...
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When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table Table 5-9. SUT1.. When applying an external clock required to avoid sudden changes in the applied ...
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To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within ...
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Table 5-10. CLKPS3 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 Clock Prescaler Select CLKPS2 CLKPS1 ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This ...
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Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept ...
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Power Reduction Register - PRR Bit Read/Write Initial Value • Bit 7 - Res: Reserved Bit This bit is unused bit in the ATmega16/32/64/M1/C1, and will always read as zero. • Bit 6 - PRCAN: Power Reduction CAN Writing ...
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Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
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Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ...
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System Control and Reset 7.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 7-1. Table 7-1. Symbol V POT V PORMAX V PORMIN V CCRR V RST Note: 7.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in The POR circuit ...
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Figure 7-2. Figure 7-3. 7.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the ...
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Brown-out Detection ATmega16/32/64/M1/C1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. ...
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Figure 7-5. 7.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t Refer to ...
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Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on ...
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Watchdog Timer ATmega16/32/64/M1/C1 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms ...
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The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during the execution of ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example C Code Example Note: Note: The Watchdog Timer should be reset before any change of the WDP ...
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Watchdog Timer Control Register - WDTCSR Bit Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con- figured for interrupt. ...
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Table 7-6. WDP3 Atmel ATmega16/32/64/M1/C1 56 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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Interrupts This section describes the specifics ATmega16/32/64/M1/C1. For a general explanation of ...
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Notes: Table 8-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical ...
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Interrupts will automatically be disabled while this sequence is executed. Interrupts are dis- abled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain ...
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I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 9-2. Note: 9.2.1 Configuring the Pin Each port pin consists of three register ...
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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn ...
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Figure 9-3. Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indi- cated by the shaded ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...
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Table 9-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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ADC4, Analog to Digital Converter, input channel 4 SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. ...
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PCINT0/MISO/PSCOUT2A – Bit 0 MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB0. When the SPI ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 9-6. Note: The alternate pin configuration is as follows: • D2A/AMP2+/PCINT15 – Bit 7 D2A, Digital to Analog output AMP2+, Analog Differential Amplifier ...
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ADC10/ACMP1/PCINT14 – Bit 6 ADC10, Analog to Digital Converter, input channel 10. ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with ...
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SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDD0 slave, the SPI is activated when this pin is driven low. When ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ACMP0/PCINT23 – Bit 7 ...
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ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the inter- nal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. INT0, External Interrupt source 0. This ...
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OC1A, Output Compare Match A output: This pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2 set “one”) to serve this function. The OC1A pin is ...
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Table 9-11. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 9.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-12. Port Pin PE2 PE1 PE0 Note: Atmel ATmega16/32/64/M1/C1 ...
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The alternate pin configuration is as follows: • PCINT26/XTAL2/ADC0 – Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be ...
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Register Description for I/O-Ports 9.4.1 Port B Data Register – PORTB Bit Read/Write Initial Value 9.4.2 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 9.4.3 Port B Input Pins Address – PINB Bit Read/Write Initial Value ...
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Port D Input Pins Address – PIND Bit Read/Write Initial Value 9.4.10 Port E Data Register – PORTE Bit Read/Write Initial Value 9.4.11 Port E Data Direction Register – DDRE Bit Read/Write Initial Value 9.4.12 Port E Input Pins ...
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External Interrupts The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23..0 pins are configured as outputs. This feature provides ...
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External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value • Bit 7..0 – ISC31, ISC30 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 ...
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External Interrupt Flag Register – EIFR Bit Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero. • Bit 3..0 – INTF3 - INTF0: External ...
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Pin Change Interrupt Flag Register - PCIFR Bit Read/Write Initial Value • Bit 7..4 - Res: Reserved Bits These bits are unused bits in the ATmega16/32/64/M1/C1, and will always read as zero. • Bit 3 - PCIF3: Pin Change ...
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Pin Change Mask Register 2 – PCMSK2 Bit Read/Write Initial Value • Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16 Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is set ...
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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Coun- ters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 11.1 Internal Clock Source The Timer/Counter can be clocked ...
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Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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Bit6 – ICPSEL1: Timer 1 Input Capture selection Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3). The selec- tion is made thanks to ICPSEL1 bit as described in Table 11- • Bit ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Out- put Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation. The main features are: • ...
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The definitions in Table 12-1. BOTTOM MAX TOP 12.1.2 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag ...
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Signal description (internal signals): count direction clear clkTn top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk source, selected by the Clock Select bits (CS02:0). When no ...
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Figure 12-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
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Figure 12-5. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the ...
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in histogram for ...
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The wave- form generated will have a maximum frequency of ...
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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to ...
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Figure 12-9 Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f (clk TCNTn TOVn Figure 12-10 mode and PWM mode, where OCR0A is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 12-11 ...
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Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 12-4 correct PWM mode. Table 12-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B ...
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Table 12-7 correct PWM mode. Table 12-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega16/32/64/M1/C1 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined ...
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Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.8.3 Timer/Counter Register – TCNT0 ...
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Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt ...
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Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Figure 13-1. 16-bit Timer/Counter Block Diagram Note: 13.1.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Regis- ter (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described ...
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The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Coun- ter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM RTG The 16-bit counter is mapped into ...
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 13.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP ...
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Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the ...
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Figure 13-4. Output Compare Unit, Block Diagram The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is ...
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Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized ...
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Figure 13-5. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode ...
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Figure 13-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn ...
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This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O loca- tion is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the ...
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The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution ...
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The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope ...
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The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA ...
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As Figure 13-9 rical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ...
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Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with ...
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Figure 13-12 and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes ...
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Timer/Counter Register Description 13.10.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B The COMnA1:0 ...
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Table 13-3 correct or the phase and frequency correct, PWM mode. Table 13-3. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the count- ing sequence ...
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Timer/Counter1 Control Register B – TCCR1B Bit Read/Write Initial Value • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from ...
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If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 13.10.3 Timer/Counter1 Control Register C ...
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Output Compare Register 1 B – OCR1BH and OCR1BL Bit Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output ...
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Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. ...
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Power Stage Controller – (PSC) (only ATmega16/32/64M1) The Power Stage Controller is a high performance waveform controller. 14.1 Features • PWM waveform generation function with 6 complementary programmable outputs (able to control 3 half-bridges) • Programmable dead time control ...
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PSC Description Figure 14-1. Power Stage Controller Block Diagram 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 PSC Counter = POCR0RB Waveform Generator B = POCR0SB Overlap = Protection POCR0RA Waveform = Generator A POCR0SA Waveform Generator B = POCR1SB Overlap Protection = POCR1RA ...
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The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is able to count top value determined by the contents of POCR_RB register and then according to the selected running mode, ...
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Figure 14-3. Cycle Presentation in Centered Mode PSC Counter Value Figure 14-2 tered Mode is like One Ramp Mode which counts down and then up. Notice that the update of the waveform generator registers is done regardless of ramp Mode ...
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Figure 14-4. PSCOUTnA & PSCOUTnB Basic Waveforms in One Ramp mode PSC Counter PSCOUTnA PSCOUTnB On-Time A = (POCRnRAH/L - POCRnSAH/L) * 1/Fclkpsc On-Time B = (POCRnRBH/L - POCRnSBH/L) * 1/Fclkpsc Dead-Time A = (POCRnSAH 1/Fclkpsc Dead-Time ...
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Figure 14-5. Controlled Start and Stop Mechanism in One-Ramp Mode POCRnRB POCRnSB POCRnRA POCRnSA PSC Counter Run PSCOUTnA PSCOUTnB Note: 14.5.3.2 Center Aligned Mode In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered. Figure 14-6. PSCOUTnA ...
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Note that in center aligned mode, POCRnRAH/L is not required ( one-ramp mode) to control PSC Output waveform timing. This allows POCRnRAH freely used to adjust ADC synchronization ( Figure 14-7. Controlled Start and Stop ...
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Value Update Synchronization New timing values or PSC output configuration can be written during the PSC cycle. Thanks to LOCK configuration bit, the new whole set of values can be taken into account after the end of the PSC ...
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Signal Description Figure 14-9. PSC External Block View Atmel ATmega16/32/64/M1/C1 144 CLK PLL CLK I/O 12 POCRRB[11:0] 12 POCR0SB[11:0] 12 POCR0RA[11:0] 12 POCR0SA[11:0] 12 POCR1SB[11:0] 12 POCR1RA[11:0] 12 POCR1SA[11:0] 12 POCR2SB[11:0] 12 POCR2RA[11:0] 12 POCR2SA[11:0] IRQ PSC PSCASY PSCOUT0A ...
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Input Description Table 14-1. POCR_RB[11:0] POCRnSB[11:0] POCRnRA[11:0] POCRnSA[11:0] CLK I/O CLK PLL AC0O AC1O AC2O Table 14-2. Name PSCIN0 PSCIN1 PSCIN2 14.8.2 Output Description Table 14-3. PSCOUT0A PSCOUT0B PSCOUT1A PSCOUT1B PSCOUT2A PSCOUT2B Table 14-4. Name IRQPSCn PSCASY Note: 7647G–AVR–09/11 ...
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PSC Input For detailed information on the PSC, please refer to Application Note ‘AVR138: PSC Cook- book’, available on the Atmel web site. Each module 0, 1 and 2 of PSC has its own system to take into account ...
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Figure 14-11. PSC Input Filterring 14.9.1.2 Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section "PSC Module n Input Control Register – PMICn", page 155. If PELEVnx ...
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PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing. Figure 14-12. PSC behaviour versus PSCn Input in Mode 001b to 10xb DT0 PSCOUTnA PSCOUTnB PSCn Input Figure 14-13. PSC behaviour versus PSCn Input A or Input B ...
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...
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Table 14-6. PCLKSELn 14.15 Interrupts This section describes the specifics ...
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PSC Register Definition Registers are explained for PSC module 0. They are identical for module 1 and module 2. 14.16.1 PSC Output Configuration – POC Bit Read/Write Initial Value • Bit 7 – not use not use • Bit ...
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PSC Synchro Configuration – PSYNC Bit Read/Write Initial Value • Bit 7 – not use not use • Bit 6 – not use not use • Bit 5:4 – PSYNC21:0: Synchronization Out for ADC Selection Select the polarity and ...
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PSC Output Compare SA Register – POCRnSAH and POCRnSAL Bit Read/Write Initial Value 14.16.4 PSC Output Compare RA Register – POCRnRAH and POCRnRAL Bit Read/Write Initial Value 14.16.5 PSCOutput Compare SB Register – POCRnSBH and POCRnSBL Bit Read/Write Initial ...
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Bit 4 – PMODE PSC Mode Select the mode of PSC. Table 14-10. PSC Mode Selection PMODE 0 1 • Bit 3 – POPB: PSC B Output Polarity If this bit is cleared, the PSC outputs B are active ...
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Bit 4:3:2 – SWAPn: SWAP Funtion Select (not implemented in ATmega32M1 up to revision C) When this bit is set; the channels PSCOUTnA and PSCOUTnB are exchanged. This allows to invert the waveforms of both channels at one time. ...
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Table 14-12. Input Mode Operation PRFMn2:0 000b 001b 010b 011b 10x 11xb 14.16.10 PSC Interrupt Mask Register – PIM Bit Read/Write Initial Value • Bit 7:4 – not use not use. • Bit 3 – PEVE2 : PSC External Event ...
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PSC Interrupt Flag Register – PIFR Bit Read/Write Initial Value • Bit 7:4 – not use not use. • Bit 3 – PEV2 : PSC External Event 2 Interrupt This bit is set by hardware when an external event ...
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Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16/32/64/M1/C1 and peripheral devices or between several AVR devices. The ATmega16/32/64/M1/C1 SPI includes the following features: 15.1 Features • Full-duplex, Three-wire Synchronous ...
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The interconnection between Master and Slave CPUs with SPI is shown in system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overrid- den according to Port Functions” on page Table 15-1. MOSI MISO Note: The following code examples show how to initialize the SPI ...
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Assembly Code Example C Code Example Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 (1) SPI_MasterInit: ; Set MOSI and SCK output, all others ...
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Assembly Code Example C Code Example Note: Atmel ATmega16/32/64/M1/C1 162 (1) SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) ldi out DDR_SPI,r17 ; Enable SPI r17,(1<<SPE) ldi SPCR,r17 out ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp ...
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SS Pin Functionality 15.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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SPI Control Register – SPCR Bit Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the ...
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These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk shown in the following table: Table 15-4. 15.2.5 SPI Status ...
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SPI Data Register – SPDR Bit Read/Write Initial Value • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to ...
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Figure 15-4. SPI Transfer Format with CPHA = 1 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = ...
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Controller Area Network - CAN The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very high level of security. The ATmega16/32/64/M1/C1 CAN controller is fully compatible with the CAN Specification 2.0 Part A and ...
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Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism, by which the dominant state overwrites the recessive state. ...
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CAN Extended Frame Figure 16-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier SOF SOF SRR IDE IDT28..18 Interframe Arbitration Space Field Remote Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space ...
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Figure 16-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Time Quantum (producer) Segments (producer) Segments (consumer) 16.2.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, ...
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Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel ...
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The bus access conflict is resolved during the arbitration field mostly over the identifier value data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote ...
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Error Signalling If one or more errors are discovered by at least one node using the above mechanisms, the current transmission is aborted by sending an "error flag". This prevents other nodes accept- ing the message and thus ensures ...
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Figure 16-5. CAN Controller Structure Buffer MOb i Buffer MOb2 Buffer MOb1 Buffer MOb0 CAN Data Buffers 16.4 CAN Channel 16.4.1 Configuration The CAN channel can be in: • Enabled mode • Standby mode • Listening mode 7647G–AVR–09/11 Atmel ATmega16/32/64/M1/C1 ...
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Figure 16-6. Listening Mode 16.4.2 Bit Timing FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quan- tum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. Field ...
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Figure 16-8. General Structure of a Bit Period CLK IO F CAN Data Notes: 1. Phase error < Phase error > Phase error > Phase error < Synchronization Segment: SYNS Tsyns=1 Tscl ...
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Figure 16-9. Overload Frame 16.5 Message Objects The MOb is a CAN frame descriptor. It contains all information to handle a CAN frame. This means that a MOb has been outlined to allow to describe a CAN message like an ...
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Tx Data & Remote Frame 1. Several fields must be initialized before sending: 2. The MOb is ready to send a data or a remote frame when the MOb configuration is 3. Then, the CAN channel scans all the ...
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Automatic Reply A reply (data frame remote frame can be automatically sent after reception of the expected remote frame. 1. Several fields must be initialized before receiving the remote frame: 2. When a remote frame matches, automatically ...
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Figure 16-10. Acceptance Filter Block Diagram internal RxDcan Note: 16.5.4 MOb Page Every MOb is mapped into a page to save place. The page number is the MOb number. This page number is set in CANPAGE register. The other numbers ...
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CAN Timer A programmable 16-bit timer is used for message stamping and time trigger communication (TTC). Figure 16-11. CAN Timer Block Diagram clk TXOK[i] RXOK[i] 16.6.1 Prescaler An 8-bit prescaler is initialized by CANTCON register. It receives the clk ...
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Error Management 16.7.1 Fault Confinement The CAN channel may be in one of the three following states: • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN ...
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AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge slot. Figure 16-13. Error Detection Procedures in a Data Frame Stuff error Form error Tx ACK error Rx Stuff error Form error CRC error 16.7.3 ...
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Figure 16-14. CAN Controller Interrupt Structure CANGIE.4 ENTX CANSTMOB.6 TXOK[i] CANSTMOB.5 RXOK[i] CANSTMOB.4 BERR[i] CANSTMOB.3 SERR[i] CANSTMOB.2 CERR[i] CANSTMOB.1 FERR[i] CANSTMOB.0 AERR[i] CANGIT.4 BXOK CANGIT.3 SERG CANGIT.2 CERG CANGIT.1 FERG CANGIT.0 AERG CANGIT.6 BOFFI CANGIT.5 OVRTIM 16.8.2 Interrupt Behavior When ...
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CAN Register Description Figure 16-15. Registers Organization AVR Registers General Control General Status General Interrupt Bit Timing 1 Bit Timing 2 Bit Timing 3 Enable MOb 2 Enable MOb 1 Enable Interrupt Enable Interrupt MOb 2 Enable Interrupt MOb ...
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General CAN Registers 16.10.1 CAN General Control Register - CANGCON Read/Write Initial Value • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. • Bit 6 – OVRQ: Overload Frame Request This is not an ...
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Bit 0 – SWRES: Software Reset Request This auto resettable bit only resets the CAN controller. 16.10.2 CAN General Status Register - CANGSTA Read/Write Initial Value • Bit 7 – Reserved Bit This bit is reserved for future use. ...
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Bit 2 – ENFG: Enable Flag This flag does not generate an interrupt. • Bit 1 – BOFF: Bus Off Mode BOFF gives the information of the state of the CAN channel. Only entering in bus off mode generates ...
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Bit 4 – BXOK: Frame Buffer Receive Interrupt Writing a logical one resets this interrupt flag. BXOK flag can be cleared only if all CONMOB fields of the MOb’s of the buffer have been re-written before. • Bit 3 ...
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Bit 5 – ENRX: Enable Receive Interrupt • Bit 4 – ENTX: Enable Transmit Interrupt • Bit 3 – ENERR: Enable MOb Errors Interrupt • Bit 2 – ENBX: Enable Frame Buffer Interrupt • Bit 1 – ENERG: Enable ...
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CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1 Read/Write Initial Value Read/Write Initial Value • Bits 5:0 - IEMOB5:0: Interrupt Enable by MOb Note: • Bit 15:6 – Reserved Bits These bits are reserved for future use. For ...
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Bit 6:1 – BRP5:0: Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the indi- vidual bit timing. Tscl If ‘BRP[5..0]=0’, see Sample Point(s)” on page • Bit 0 – Reserved Bit ...
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CAN Bit Timing Register 3 - CANBT3 Read/Write Initial Value • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written. • Bit ...
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CAN Timer Registers - CANTIML and CANTIMH Bit Bit Read/Write Initial Value • Bits 15:0 - CANTIM15:0: CAN Timer Count CAN timer counter range 0 to 65,535. 16.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH Read/Write Initial Value ...
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Bit 3:0 – CGP3:0: CAN General Purpose Bits These bits can be pre-programmed to match with the wanted configuration of the CANPAGE register (i.e., AINC and INDX2:0 setting). 16.10.17 CAN Page MOb Register - CANPAGE Read/Write Initial Value • ...
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Bit 4 – BERR: Bit Error (Only in Transmission) This flag can generate an interrupt. It must be cleared using a read-modify-write software rou- tine on the whole CANSTMOB register. The bit value monitored is different from the bit ...
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These bits are not cleared once the communication is performed. The user must re-write the configuration to enable a new communication. • This operation is necessary to be able to reset the BXOK flag. • This operation also set the ...
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V2.0 part A • Bit 31:21 – IDT10:0: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. • Bit 20:3 – Reserved ...
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CAN Identifier Mask Registers - CANIDM1, CANIDM2, CANIDM3, and CANIDM4 Read/Write Initial Value Read/Write Initial Value V2.0 part A • Bit 31:21 – IDMSK10:0: Identifier Mask • Bit 20:3 – Reserved Bits These bits are reserved for future use. ...