ATmega48 Automotive Atmel Corporation, ATmega48 Automotive Datasheet - Page 114

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ATmega48 Automotive

Manufacturer Part Number
ATmega48 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega48 Automotive

Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
114
Atmel ATtiny24/44/84 [Preliminary]
Table 14-3
correct or the phase and frequency correct, PWM mode.
Table 14-3.
Note:
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation is to be used, see
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match
(CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see
ation” on page
COM1A1/COM1B1
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
“Phase Correct PWM Mode” on page 107
0
0
1
1
shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
103).
(Note:)
COM1A0/COM1B0
0
1
0
1
Table 14-4 on page
Description
Normal port operation, OC1A/OC1B disconnected.
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
Clear OC1A/OC1B on Compare Match when
up-counting. Set OC1A/OC1B on Compare Match
when downcounting.
Set OC1A/OC1B on Compare Match when
up-counting. Clear OC1A/OC1B on Compare Match
when downcounting.
for more details.
115. Modes of operation sup-
“Modes of Oper-
7701E–AVR–02/11

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