ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 83

• Manufacturer Part Number: ATmega8515
• Manufacturer: Atmel Corporation

Specifications of ATmega8515

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Force Output Compare
Compare Match Blocking by
TCNT0 Write
Using the Output Compare
Unit
2512K–AVR–01/10
The OCR0 Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR0 Compare Register to either top or bottom of the counting sequence. The synchro-
nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0 Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double
buffering is disabled the CPU will access the OCR0 directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC0) bit. Forcing Compare
Match will not set the OCF0 Flag or reload/clear the timer, but the OC0 pin will be
updated as if a real Compare Match had occurred (the COM01:0 bits settings define
whether the OC0 pin is set, cleared or toggled).
All CPU write operations to the TCNT0 Register will block any Compare Match that
occur in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when
the Timer/Counter clock is enabled.
Since writing TCNT0 in any mode of operation will block all Compare Matches for one
timer clock cycle, there are risks involved when changing TCNT0 when using the output
compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT0 equals the OCR0 value, the Compare Match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC0 should be performed before setting the Data Direction Register for
the port pin to output. The easiest way of setting the OC0 value is to use the Force Out-
put Compare (FOC0) strobe bits in Normal mode. The OC0 Register keeps its value
even when changing between Waveform Generation modes.
Be aware that the COM01:0 bits are not double buffered together with the compare
value. Changing the COM01:0 bits will take effect immediately.
ATmega8515(L)
83