ATtiny4 Atmel Corporation, ATtiny4 Datasheet - Page 35
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ATtiny4
Manufacturer Part Number
ATtiny4
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny4
Flash (kbytes)
0.5 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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8.4.3
8127E–AVR–11/11
RSTFLR – Reset Flag Register
• Bits 2:0 – VLM2:0: Trigger Level of Voltage Level Monitor
These bits set the trigger level for the voltage level monitor, as described in
Table 8-4.
For VLM voltage levels, see
The Reset Flag Register provides information on which reset source caused an MCU Reset.
• Bits 7:4, 2– Res: Reserved Bits
These bits are reserved bits in ATtiny4/5/9/10 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
Bit
0x3B
Read/Write
Initial Value
VLM2:0
000
001
010
011
100
101
110
111
Setting the Trigger Level of Voltage Level Monitor.
R
7
–
0
VLM1H
VLM1L
Label
VLM0
VLM2
VLM3
R
6
–
0
Table 16-6 on page
R
5
–
0
Description
Voltage Level Monitor disabled
Triggering generates a regular Power-On Reset (POR).
The VLM flag is not set
Triggering sets the VLM Flag (VLMF) and generates a VLM
interrupt, if enabled
R
4
–
0
WDRF
R/W
120.
X
3
Not allowed
R
2
–
0
EXTRF
R/W
X
1
ATtiny4/5/9/10
PORF
R/W
X
0
Table 8-4
RSTFLR
below.
35