ATtiny4 Atmel Corporation, ATtiny4 Datasheet - Page 55
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ATtiny4
Manufacturer Part Number
ATtiny4
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny4
Flash (kbytes)
0.5 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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11.3
11.3.1
11.3.1.1
8127E–AVR–11/11
Clock Sources
Prescaler
Prescaler Reset
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter control Register B (TCCR0B). For details on clock sources and
prescaler, see section “Prescaler”.
The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source.
See
Figure 11-2. Prescaler for Timer/Counter0
Note:
The prescaled clock has a frequency of f
Table 11-6 on page 77
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for
situations where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (CS2:0 = 2, 3, 4, or 5). The number of system
PSR10
clk
T0
I/O
Figure 11-2
1. The synchronization logic on the input pins (
Synchronization
for an illustration of the prescaler unit.
CLK_I/O
for details.
). Alternatively, one of four taps from the prescaler can be used as a
Clear
CLK_I/O
/8, f
T0)
CLK_I/O
is shown in
/64, f
CLK_I/O
Figure 11-3 on page
ATtiny4/5/9/10
/256, or f
clk
T0
CLK_I/O
56.
/1024. See
55