ATtiny44 Automotive Atmel Corporation, ATtiny44 Automotive Datasheet - Page 129
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATtiny44 Automotive
Manufacturer Part Number
ATtiny44 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny44 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
14
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
6
Hardware Qtouch Acquisition
No
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16.3.5
16.3.6
16.4
16.4.1
16.4.2
16.4.3
16.4.4
16.4.5
7701E–AVR–02/11
Alternative USI Usage
Start Condition Detector
Clock speed considerations
Half-duplex Asynchronous Data Transfer
4-bit Counter
12-bit Timer/Counter
Edge-Triggered External Interrupt
Software Interrupt
The start condition detector is shown in
the range of 50 to 300ns) to ensure valid sampling of the SCL line. The start condition detector
is only enabled in two-wire mode.
The start condition detector is working asynchronously, and can, therefore, wake up the pro-
cessor from the power-down sleep mode. However, the protocol used might have restrictions
on the SCL hold time. Therefore, when using this feature in this case, the oscillator start-up
time set by the CKSEL fuses (see
also be taken into consideration. See the USISIF bit description in
ister” on page 130
Maximum frequency for SCL and SCK is f
receive rate in both two- and three-wire mode. In two-wire slave mode the two-wire clock con-
trol unit will hold SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact
and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F), it can function as an additional external interrupt.
The overflow flag and interrupt enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
for further details.
Atmel ATtiny24/44/84 [Preliminary]
“Clock Systems and their Distribution” on page
Figure 16-6 on page
CK
/4. This is also the maximum data transmit and
128. The SDA line is delayed (in
“USISR – USI Status Reg-
25) must
129
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