ATxmega128A3 Atmel Corporation, ATxmega128A3 Datasheet - Page 73
ATxmega128A3
Manufacturer Part Number
ATxmega128A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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6.8.2
8077H–AVR–12/09
CHnCTRL – Event Channel n Control Register
.
• Bit 7 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 6:5 - QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals where a valid
index signal is recognized and the counter index data event is given according to
page
nal is used.
These bits are only available for CH0CTRL, CH2CTRL and CH4CTRL
Table 6-5.
• Bit 4 - QDIEN: Quadrature Decode Index Enable
When this bit is set the event channel will be used as QDEC index source, and the index data
event will be enabled.
These bit is only available for CH0CTRL, CH2CTRL and CH4CTRL.
• Bit 3 - QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
These bits is only available for CH0CTRL, CH2CTRL and CH4CTRL.
• Bit 2:0 - DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event
channel only when the event source has been active and sampled with the same level for a a
number of peripheral clock for the number of cycles as defined by DIGFILT.
Bit
Read/Write
Initial Value
QDIRM[1:0]
0
0
1
1
73. These bits is only needed to set when a quadrature encoed with a connected index sig-
0
1
0
1
QDIRM Bit Settings
7
R
0
-
Index Recognition State
{QDPH0, QDPH90} = 0b00
{QDPH0, QDPH90} = 0b01
{QDPH0, QDPH90} = 0b10
{QDPH0, QDPH90} = 0b11
R/W
6
0
QDIRM[1:0]
R/W
5
0
QDIEN
R/W
4
0
QDEN
R/W
3
0
R/W
2
0
DIGFILT[2:0]
R/W
1
0
XMEGA A
R
0
0
Table 6-5 on
CHnCTRL
73
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